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74LVTH273WMX
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The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.5 ns |
| Height Seated (Max) | 2.642mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LVTH273WMX Overview
In the form of 20-SOIC (0.295, 7.50mm Width), it has been packaged. The package Tape & Reel (TR)contains it. T flip flop uses Non-Invertedas the output. Positive Edgeis the trigger it is configured with. There is an electronic component mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. It is at -40°C~85°C TAdegrees Celsius that the system is operating. It is an electronic flip flop with the type D-Type. In terms of FPGAs, it belongs to the 74LVTH series. It should not exceed 150MHzin its output frequency. D latch consists of 1 elements. This process consumes 190μA quiescents. 20terminations have occurred. A voltage of 3V is used to power it. A JK flip flop with a 3pFfarad input capacitance is used here. In this case, the D flip flop belongs to the LVTfamily. Vsup reaches 3.6V, the maximal supply voltage. It is imperative that the supply voltage (Vsup) is maintained above 2.7Vin order to ensure normal operation.
74LVTH273WMX Features
Tape & Reel (TR) package
74LVTH series
74LVTH273WMX Applications
There are a lot of Rochester Electronics, LLC 74LVTH273WMX Flip Flops applications.
- Data storage
- Consumer
- Balanced Propagation Delays
- Digital electronics systems
- Computers
- 2 – Bit synchronous counter
- Convert a momentary switch to a toggle switch
- Guaranteed simultaneous switching noise level
- Set-reset capability
- Divide a clock signal by 2 or 4