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5M570ZE64I5N

PMIC MAX? V Series 64-TQFP Exposed Pad


  • Manufacturer: Intel
  • Origchip NO: 386-5M570ZE64I5N
  • Package: 64-TQFP Exposed Pad
  • Datasheet: PDF
  • Stock: 917
  • Description: PMIC MAX? V Series 64-TQFP Exposed Pad (Kg)

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Shipping Cost

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The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

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Currently, our products are shipped through DHL, FedEx, SF, and UPS.

Delivery Time

Once the goods are shipped, estimated delivery time depends on the shipping methods you chose:

FedEx International, 5-7 business days.

The following are some common countries' logistic time.
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Details

Tags

Parameters
Factory Lead Time 8 Weeks
Mounting Type Surface Mount
Package / Case 64-TQFP Exposed Pad
Operating Temperature -40°C~100°C TJ
Packaging Tray
Series MAX® V
Part Status Active
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Programmable Type In System Programmable
Number of I/O 54
Number of Macro Cells 440
Voltage Supply - Internal 1.71V~1.89V
Delay Time tpd(1) Max 9ns
Number of Logic Elements/Blocks 570
RoHS Status RoHS Compliant

5M570ZE64I5N Overview


This network has 440macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).64-TQFP Exposed Padis the package in which it resides.This device has 54 I/O ports programmed into it.Trayis the packaging method.A reliable operation is ensured by the operating temperature of [0].It is mounted in the way of Surface Mount.This type of FPGA is a part of the MAX? V series.In total, there are 570 logic elements/blocks.

5M570ZE64I5N Features


64-TQFP Exposed Pad package
54 I/Os
The operating temperature of -40°C~100°C TJ

5M570ZE64I5N Applications


There are a lot of Intel 5M570ZE64I5N CPLDs applications.

  • High speed graphics processing
  • Power automation
  • Digital multiplexers
  • INTERRUPT SYSTEM
  • Configurable Addressing of I/O Boards
  • I2C BUS INTERFACE
  • Page register
  • DDC INTERFACE
  • Reset swapping
  • Custom state machines