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74AUP2G79DC-Q100H

0.8V~3.6V 309MHz D-Type Flip Flop DUAL 74AUP2G79 8 Pins 74AUP Series 8-VFSOP (0.091, 2.30mm Width)


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74AUP2G79DC-Q100H
  • Package: 8-VFSOP (0.091, 2.30mm Width)
  • Datasheet: PDF
  • Stock: 209
  • Description: 0.8V~3.6V 309MHz D-Type Flip Flop DUAL 74AUP2G79 8 Pins 74AUP Series 8-VFSOP (0.091, 2.30mm Width)(Kg)

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FedEx International, 5-7 business days.

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Details

Tags

Parameters
Factory Lead Time 8 Weeks
Contact Plating Gold
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-VFSOP (0.091, 2.30mm Width)
Number of Pins 8
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Published 2013
Series 74AUP
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type D-Type
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) NOT SPECIFIED
Supply Voltage 1.1V
Terminal Pitch 0.5mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Base Part Number 74AUP2G79
Function Standard
Output Type Non-Inverted
Polarity Non-Inverting
Supply Voltage-Max (Vsup) 3.6V
Clock Frequency 309MHz
Propagation Delay 5.8 ns
Quiescent Current 500nA
Turn On Delay Time 8.5 ns
Family AUP/ULP/V
Logic Function D-Type, Flip-Flop
Current - Output High, Low 4mA 4mA
Number of Bits per Element 1
Max Propagation Delay @ V, Max CL 5.8ns @ 3.3V, 30pF
Trigger Type Positive Edge
Input Capacitance 0.6pF
Number of Input Lines 2
Clock Edge Trigger Type Positive Edge
RoHS Status ROHS3 Compliant

74AUP2G79DC-Q100H Overview


As a result, it is packaged as 8-VFSOP (0.091, 2.30mm Width). It is contained within the Tape & Reel (TR)package. T flip flop uses Non-Invertedas the output. It is configured with a trigger that uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. The supply voltage is set to 0.8V~3.6V. It is operating at -40°C~125°C TA. It is an electronic flip flop with the type D-Type. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. This D flip flop should not have a frequency greater than 309MHz. It has been determined that there have been 8 terminations. It is a member of the 74AUP2G79 family. Power is provided by a 1.1V supply. The input capacitance of this JK flip flopis 0.6pF farads. AUP/ULP/Vis the family of this D flip flop. The electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 8. This device has Positive Edgeas its clock edge trigger type. As soon as 3.6Vis reached, Vsup reaches its maximum value. The number of input lines is 2. 500nAquiescent current consumed.

74AUP2G79DC-Q100H Features


Tape & Reel (TR) package
74AUP series
8 pins

74AUP2G79DC-Q100H Applications


There are a lot of Nexperia USA Inc. 74AUP2G79DC-Q100H Flip Flops applications.

  • Counters
  • Pattern generators
  • Supports Live Insertion
  • Frequency division
  • Automotive
  • Dynamic threshold performance
  • ATE
  • Matched Rise and Fall
  • Modulo – n – counter
  • Single Up Count-Control Line