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  • 74LV374N,112

74LV374N,112

1V~5.5V 70MHz D-Type Flip Flop DUAL 74LV374 20μA 74LV Series 20-DIP (0.300, 7.62mm)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV374N,112
  • Package: 20-DIP (0.300, 7.62mm)
  • Datasheet: PDF
  • Stock: 759
  • Description: 1V~5.5V 70MHz D-Type Flip Flop DUAL 74LV374 20μA 74LV Series 20-DIP (0.300, 7.62mm)(Kg)

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Details

Tags

Parameters
Mounting Type Through Hole
Package / Case 20-DIP (0.300, 7.62mm)
Surface Mount NO
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 2009
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 2.54mm
Reach Compliance Code unknown
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV374
JESD-30 Code R-PDIP-T20
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 70MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 20μA
Output Characteristics 3-STATE
Current - Output High, Low 16mA 16mA
Output Polarity TRUE
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 20ns @ 5V, 50pF
Prop. Delay@Nom-Sup 29 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 49 ns
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 4.2mm
Length 26.73mm
Width 7.62mm
RoHS Status ROHS3 Compliant

74LV374N,112 Overview


In the form of 20-DIP (0.300, 7.62mm), it has been packaged. A package named Tubeincludes it. This output is configured with Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. This electronic part is mounted in the way of Through Hole. It operates with a supply voltage of 1V~5.5V. The operating temperature is -40°C~125°C TA. It is an electronic flip flop with the type D-Type. In FPGA terms, D flip flop is a type of 74LVseries FPGA. It should not exceed 70MHzin terms of its output frequency. A total of 1 elements are present. As a result, it consumes 20μA of quiescent current without being affected by external factors. It has been determined that there have been 20 terminations. D latch belongs to the 74LV374 family. The D flip flop is powered by a voltage of 3.3V . Input capacitance of this device is 3.5pF farads. It is a member of the LV/LV-A/LVX/Hfamily of D flip flop. There is a base part number FF/Latchesfor the RS flip flops. It reaches 5.5Vwhen the supply voltage is maximal (Vsup). Keeping the supply voltage (Vsup) above 1V is necessary for normal operation. It operates from 3.3V power supplies. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.

74LV374N,112 Features


Tube package
74LV series
3.3V power supplies

74LV374N,112 Applications


There are a lot of NXP USA Inc. 74LV374N,112 Flip Flops applications.

  • Asynchronous counter
  • Convert a momentary switch to a toggle switch
  • Safety Clamp
  • Registers
  • Computers
  • Memory
  • CMOS Process
  • Parallel data storage
  • 2 – Bit synchronous counter
  • Power down protection