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  • 74LV574D,118

74LV574D,118

1V~5.5V 70MHz D-Type Flip Flop DUAL 74LV574 20μA 74LV Series 20-SOIC (0.295, 7.50mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV574D,118
  • Package: 20-SOIC (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 274
  • Description: 1V~5.5V 70MHz D-Type Flip Flop DUAL 74LV574 20μA 74LV Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-SOIC (0.295, 7.50mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Published 2002
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Additional Feature BROADSIDE VERSION OF 374
Subcategory FF/Latches
Packing Method TAPE AND REEL
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV574
JESD-30 Code R-PDSO-G20
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 70MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 20μA
Output Characteristics 3-STATE
Current - Output High, Low 16mA 16mA
Output Polarity TRUE
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 17ns @ 5V, 50pF
Prop. Delay@Nom-Sup 25 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 43 ns
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 2.65mm
Width 7.5mm
RoHS Status ROHS3 Compliant

74LV574D,118 Overview


20-SOIC (0.295, 7.50mm Width)is the way it is packaged. A package named Tape & Reel (TR)includes it. As configured, the output uses Tri-State, Non-Inverted. JK flip flop uses Positive Edgeas the trigger. Surface Mountis in the way of this electric part. A supply voltage of 1V~5.5V is required for operation. -40°C~125°C TAis the operating temperature. This logic flip flop is classified as type D-Type. In FPGA terms, D flip flop is a type of 74LVseries FPGA. A frequency of 70MHzshould be the maximum output frequency. The element count is 1 . This process consumes 20μA quiescents. 20terminations have occurred. The 74LV574family includes it. The power supply voltage is 3.3V. There is 3.5pF input capacitance for this T flip flop. It is a member of the LV/LV-A/LVX/Hfamily of D flip flop. The part is included in FF/Latches. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. The supply voltage (Vsup) should be maintained above 1V for normal operation. In view of its reliability, this D flip flop is a good fit for TAPE AND REEL. There are 3.3V power supplies attached to it. This D flip flop is equipped with 0 ports. Additionally, there are BROADSIDE VERSION OF 374 on the electronic flip flop that can be referred to.

74LV574D,118 Features


Tape & Reel (TR) package
74LV series
3.3V power supplies

74LV574D,118 Applications


There are a lot of NXP USA Inc. 74LV574D,118 Flip Flops applications.

  • Matched Rise and Fall
  • Consumer
  • Individual Asynchronous Resets
  • Instrumentation
  • Supports Live Insertion
  • Digital electronics systems
  • Divide a clock signal by 2 or 4
  • Computers
  • Control circuits
  • Data transfer