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74LV574DB,112

1V~5.5V 70MHz D-Type Flip Flop DUAL 74LV574 20μA 74LV Series 20-SSOP (0.209, 5.30mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV574DB,112
  • Package: 20-SSOP (0.209, 5.30mm Width)
  • Datasheet: PDF
  • Stock: 745
  • Description: 1V~5.5V 70MHz D-Type Flip Flop DUAL 74LV574 20μA 74LV Series 20-SSOP (0.209, 5.30mm Width)(Kg)

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Details

Tags

Parameters
Terminal Finish NICKEL PALLADIUM GOLD
Additional Feature BROADSIDE VERSION OF 374
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV574
JESD-30 Code R-PDSO-G20
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 70MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 20μA
Output Characteristics 3-STATE
Current - Output High, Low 16mA 16mA
Output Polarity TRUE
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 17ns @ 5V, 50pF
Prop. Delay@Nom-Sup 25 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 43 ns
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 2mm
Length 7.2mm
Width 5.3mm
RoHS Status ROHS3 Compliant
Mounting Type Surface Mount
Package / Case 20-SSOP (0.209, 5.30mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 2009
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type

74LV574DB,112 Overview


It is packaged in the way of 20-SSOP (0.209, 5.30mm Width). There is an embedded version in the package Tube. There is a Tri-State, Non-Invertedoutput configured with it. There is a trigger configured with Positive Edge. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 1V~5.5V volts, it operates. In this case, the operating temperature is -40°C~125°C TA. This D latch has the type D-Type. The FPGA belongs to the 74LV series. It should not exceed 70MHzin terms of its output frequency. In total, it contains 1 elements. There is a consumption of 20μAof quiescent energy. It has been determined that there have been 20 terminations. JK flip flop belongs to 74LV574 family. A voltage of 3.3V is used as the power supply for this D latch. This JK flip flop has a 3.5pFfarad input capacitance. It belongs to the family of electronic devices known as LV/LV-A/LVX/H. This device has the base part number FF/Latches. It reaches 5.5Vwhen the maximum supply voltage (Vsup) is applied. It is imperative that the supply voltage (Vsup) is maintained above 1Vin order to ensure normal operation. An electrical current of 3.3V volts is applied to it. There are 2 ports embedded in the flip flops. In addition, you can refer to the additinal BROADSIDE VERSION OF 374 of the D latch.

74LV574DB,112 Features


Tube package
74LV series
3.3V power supplies

74LV574DB,112 Applications


There are a lot of NXP USA Inc. 74LV574DB,112 Flip Flops applications.

  • Memory
  • Dynamic threshold performance
  • Frequency Dividers
  • Consumer
  • Convert a momentary switch to a toggle switch
  • Single Up Count-Control Line
  • Buffer registers
  • Balanced Propagation Delays
  • Functionally equivalent to the MC10/100EL29
  • Frequency division