English

All Products

View All >>
  • 74VHC374FT

74VHC374FT

2V~5.5V 120MHz D-Type Flip Flop DUAL 4μA 74VHC Series 20-TSSOP (0.173, 4.40mm Width)


  • Manufacturer: Toshiba Semiconductor and Storage
  • Origchip NO: 830-74VHC374FT
  • Package: 20-TSSOP (0.173, 4.40mm Width)
  • Datasheet: PDF
  • Stock: 844
  • Description: 2V~5.5V 120MHz D-Type Flip Flop DUAL 4μA 74VHC Series 20-TSSOP (0.173, 4.40mm Width)(Kg)

Purchase & Inquiry

Transport

Purchase

You may place an order without registering to Utmel.
We strongly suggest you sign in before purchasing as you can track your order in real time.

Means of Payment

For your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and wire transfer.

RFQ (Request for Quotations)

It is recommended to request for quotations to get the latest prices and inventories about the part.
Our sales will reply to your request by email within 24 hours.

IMPORTANT NOTICE

1. You'll receive an order information email in your inbox. (Please remember to check the spam folder if you didn't hear from us).
2. Since inventories and prices may fluctuate to some extent, the sales manager is going to reconfirm the order and let you know if there are any updates.

Shipping Cost

Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.)
The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

Shipping Method

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

Delivery Time

Once the goods are shipped, estimated delivery time depends on the shipping methods you chose:

FedEx International, 5-7 business days.

The following are some common countries' logistic time.
transport

Details

Tags

Parameters
Factory Lead Time 12 Weeks
Mounting Type Surface Mount
Package / Case 20-TSSOP (0.173, 4.40mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Series 74VHC
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Technology CMOS
Voltage - Supply 2V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) NOT SPECIFIED
Supply Voltage 5V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
JESD-30 Code R-PDSO-G20
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Supply Voltage-Min (Vsup) 2V
Number of Ports 2
Clock Frequency 120MHz
Family AHC/VHC/H/U/V
Current - Quiescent (Iq) 4μA
Output Characteristics 3-STATE
Current - Output High, Low 8mA 8mA
Output Polarity TRUE
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 10.1ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4pF
Length 6.5mm
Width 4.4mm
RoHS Status RoHS Compliant

74VHC374FT Overview


20-TSSOP (0.173, 4.40mm Width)is the way it is packaged. As part of the package Tape & Reel (TR), it is embedded. In the configuration, Tri-State, Non-Invertedis used as the output. This trigger uses the value Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 2V~5.5V. It is operating at a temperature of -40°C~125°C TA. This logic flip flop is classified as type D-Type. This type of FPGA is a part of the 74VHC series. A frequency of 120MHzshould be the maximum output frequency. In total, there are 1 elements. There is a consumption of 4μAof quiescent energy. There have been 20 terminations. Power is supplied from a voltage of 5V volts. A JK flip flop with a 4pFfarad input capacitance is used here. It is a member of the AHC/VHC/H/U/Vfamily of D flip flop. It reaches the maximum supply voltage (Vsup) at 5.5V. Normal operation requires a supply voltage (Vsup) above 2V. The flip flop contains 2ports.

74VHC374FT Features


Tape & Reel (TR) package
74VHC series

74VHC374FT Applications


There are a lot of Toshiba Semiconductor and Storage 74VHC374FT Flip Flops applications.

  • Safety Clamp
  • Frequency division
  • Balanced Propagation Delays
  • Divide a clock signal by 2 or 4
  • Patented noise
  • Single Up Count-Control Line
  • Guaranteed simultaneous switching noise level
  • Asynchronous counter
  • Bounce elimination switch
  • Dynamic threshold performance