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  • EPM3512AFI256-10N

EPM3512AFI256-10N

1mm PMIC 256 Pin 125MHz 3.3V FBGA


  • Manufacturer: Altera
  • Origchip NO: 2936-EPM3512AFI256-10N
  • Package: FBGA
  • Datasheet: PDF
  • Stock: 886
  • Description: 1mm PMIC 256 Pin 125MHz 3.3V FBGA (Kg)

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Details

Tags

Parameters
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 1mm
Frequency 125MHz
Time@Peak Reflow Temperature-Max (s) 40
Pin Count 256
Qualification Status Not Qualified
Operating Supply Voltage 3.3V
Temperature Grade INDUSTRIAL
Max Supply Voltage 3.6V
Min Supply Voltage 3V
Number of I/O 208
Memory Type EEPROM
Propagation Delay 10 ns
Turn On Delay Time 10 ns
Frequency (Max) 116.3MHz
Programmable Logic Type EE PLD
Number of Gates 10000
Number of Programmable I/O 208
Number of Logic Blocks (LABs) 32
Output Function MACROCELL
Number of Macro Cells 512
JTAG BST YES
In-System Programmable YES
Height Seated (Max) 3.5mm
Length 17mm
Width 17mm
RoHS Status RoHS Compliant
Lead Free Lead Free
Factory Lead Time 10 Weeks
Mount Surface Mount
Package / Case FBGA
Number of Pins 256
Published 1996
JESD-609 Code e1
Pbfree Code yes
Moisture Sensitivity Level (MSL) 3
Number of Terminations 256
ECCN Code 3A991
Terminal Finish Tin/Silver/Copper (Sn/Ag/Cu)
Max Operating Temperature 85°C
Min Operating Temperature -40°C
Additional Feature YES
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position BOTTOM
Terminal Form BALL

EPM3512AFI256-10N Overview


There are 512 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is embedded in the FBGA package.There are 208 I/Os programmed in it.There are 256 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.This electrical part has a terminal position of BOTTOMand is connected to the ground.It is powered from a supply voltage of 3.3V.It is a part of the family [0].There are 256 pins on the chip.If you use this device, you will also find [0].A digital circuit is built using 10000gates.High efficiency requires the supply voltage to be maintained at [0].For storing data, it is recommended to use [0].In this case, it is mounted by Surface Mount.A total of 256pins are provided on this board.It operates with the maximal supply voltage of 3.6V.Normally, it operates with a voltage of 3VV as its minimum supply voltage.There are 208 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. This frequency can be achieved at 125MHz.Operating temperatures should be higher than 0°C.A temperature less than 85°Cshould be used for operation.The logic block consists of 32 l logic blocks (LABs).If the maximal frequency is less than [0], it should be lower than that.Types of programmable logic are divided into EE PLD.

EPM3512AFI256-10N Features


FBGA package
208 I/Os
256 pin count
256 pins
32 logic blocks (LABs)

EPM3512AFI256-10N Applications


There are a lot of Altera EPM3512AFI256-10N CPLDs applications.

  • I/O expansion
  • POWER-SAVING MODES
  • Synchronous or asynchronous mode
  • I/O PORTS (MCU MODULE)
  • Wireless Infrastructure Base Band Unit and Remote Radio Unit
  • Address decoding
  • ANALOG-TO-DIGITAL CONVERTOR (ADC)
  • Custom shift registers
  • Field programmable gate
  • Wide Vin Industrial low power SMPS