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  • EPM7256BQC208-10

EPM7256BQC208-10

1.8/3.32.5V 0.5mm PMIC 208 Pin 125MHz 2.5V PQFP


  • Manufacturer: Altera
  • Origchip NO: 2936-EPM7256BQC208-10
  • Package: PQFP
  • Datasheet: PDF
  • Stock: 866
  • Description: 1.8/3.32.5V 0.5mm PMIC 208 Pin 125MHz 2.5V PQFP (Kg)

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Details

Tags

Parameters
Factory Lead Time 8 Weeks
Mount Surface Mount
Package / Case PQFP
Number of Pins 208
Published 1998
JESD-609 Code e0
Pbfree Code no
Part Status Discontinued
Moisture Sensitivity Level (MSL) 3
Number of Terminations 208
ECCN Code 3A991
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature 70°C
Min Operating Temperature 0°C
Additional Feature YES
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 220
Supply Voltage 2.5V
Terminal Pitch 0.5mm
Frequency 125MHz
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 208
Qualification Status Not Qualified
Power Supplies 1.8/3.32.5V
Temperature Grade COMMERCIAL
Max Supply Voltage 3.6V
Min Supply Voltage 3V
Memory Type EEPROM
Propagation Delay 10 ns
Turn On Delay Time 10 ns
Frequency (Max) 188.7MHz
Organization 0 DEDICATED INPUTS
Programmable Logic Type EE PLD
Number of Gates 5000
Number of Programmable I/O 164
Number of Logic Blocks (LABs) 16
Speed Grade 10
Output Function MACROCELL
Number of Macro Cells 256
JTAG BST YES
In-System Programmable YES
Height Seated (Max) 4.1mm
Length 28mm
Width 28mm
RoHS Status RoHS Compliant

EPM7256BQC208-10 Overview


In the mobile phone network, there are 256macro cells, which are cells with high-power antennas and towers.It is contained in package [0].The termination of a device is set to [0].This electrical component has a terminal position of 0.A voltage of 2.5V is used as the power supply for this device.It is a part of family [0].In this chip, the 208pins are programmed.Additionally, this device is capable of displaying [0].As a building block for digital circuits, there are 5000gates.It is adopted to store data in [0].In this case, Surface Mountis used to mount the electronic component.There are 208 pins on the device.A maximum voltage of 3.6Vis required for operation.The device is designed to operate with a minimal supply voltage of 3VV.Currently, it is powered by 1.8/3.32.5Vsources.There are 164 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. There is 125MHz frequency that can be achieved.It is recommended that the operating temperature be greater than 0°C.It is recommended that the operating temperature be lower than 70°C.The system consists of 16 logic blocks (LABs).Maximum frequency should be less than 188.7MHz.There is a type of programmable logic called EE PLD.

EPM7256BQC208-10 Features


PQFP package
208 pin count
208 pins
1.8/3.32.5V power supplies
16 logic blocks (LABs)

EPM7256BQC208-10 Applications


There are a lot of Altera EPM7256BQC208-10 CPLDs applications.

  • Reset swapping
  • PLC analog input modules
  • Bootloaders for FPGAs
  • Boolean function generators
  • USB Bus
  • Pattern recognition
  • Field programmable gate
  • I/O expansion
  • POWER-SAVING MODES
  • High speed graphics processing