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EPM9320ARC208-10N

0.5mm PMIC 208 Pin 5V

Manufacturer: Altera
Origchip NO: 2936-EPM9320ARC208-10N
Package: -
Datasheet: PDF
Stock: 253
Description: 0.5mm PMIC 208 Pin 5V (Kg)

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Details

Tags

Parameters
Mount	Surface Mount
Number of Pins	208
Published	1994
JESD-609 Code	e2
Pbfree Code	yes
Part Status	Discontinued
Moisture Sensitivity Level (MSL)	3
Number of Terminations	208
ECCN Code	EAR99
Terminal Finish	Matte Tin/Copper (Sn/Cu)
Max Operating Temperature	70°C
Min Operating Temperature	0°C
HTS Code	8542.39.00.01
Technology	CMOS
Terminal Position	QUAD
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	245
Supply Voltage	5V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	40
Pin Count	208
Qualification Status	Not Qualified
Operating Supply Voltage	5V
Temperature Grade	COMMERCIAL
Max Supply Voltage	5.25V
Min Supply Voltage	4.75V
Number of I/O	132
Memory Type	EEPROM
Clock Frequency	144.9MHz
Propagation Delay	10.8 ns
Programmable Logic Type	EE PLD
Number of Gates	6000
Number of Logic Blocks (LABs)	20
Output Function	MACROCELL
Number of Macro Cells	320
Height Seated (Max)	4.1mm
Length	28mm
Width	28mm
RoHS Status	RoHS Compliant

EPM9320ARC208-10N Overview

This network has 320macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).There are 132 I/Os programmed in it.There is a 208terminations set on devices.This electrical part is wired with a terminal position of QUAD.The power source is powered by 5Vvolts.208pins are programmed on the chip.In digital circuits, 6000gates serve as building blocks.High efficiency requires a voltage supply of [0].It is recommended that data be stored in [0].It is mounted by Surface Mount.The device is designed with pins [0].A voltage of 5.25V is the maximum supply voltage for this device.With a minimal supply voltage of [0], it operates.It is recommended that the operating temperature be higher than 0°C.It is recommended to keep the operating temperature below 70°C.20logic blocks (LABs) make up this circuit.Ideally, its clock frequency should not exceed 144.9MHz.There is a type of programmable logic called EE PLD.

EPM9320ARC208-10N Features

132 I/Os
208 pin count
208 pins
20 logic blocks (LABs)

EPM9320ARC208-10N Applications

There are a lot of Altera EPM9320ARC208-10N CPLDs applications.

ToR/Aggregation/Core Switch and Router
Custom state machines
Configurable Addressing of I/O Boards
Preset swapping
Complex programmable logic devices
Protection relays
USB Bus
Code converters
Wireless Infrastructure Base Band Unit and Remote Radio Unit
Boolean function generators