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SN74AUC1G80YEAR
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| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 5-XFBGA, DSBGA |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUC |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 5 |
| Type | D-Type |
| Terminal Finish | TIN LEAD |
| Technology | CMOS |
| Voltage - Supply | 0.8V~2.7V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-XBGA-B5 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 2.7V |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 275MHz |
| Family | AUC |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 9mA 9mA |
| Max Propagation Delay @ V, Max CL | 1.8ns @ 2.5V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| Propagation Delay (tpd) | 3.9 ns |
| fmax-Min | 275 MHz |
| Height Seated (Max) | 0.5mm |
| Width | 0.9mm |
| RoHS Status | Non-RoHS Compliant |
SN74AUC1G80YEAR Overview
It is packaged in the way of 5-XFBGA, DSBGA. D flip flop is embedded in the Tape & Reel (TR) package. Invertedis the output configured for it. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Surface Mount. A voltage of 0.8V~2.7Vis used as the supply voltage. Currently, the operating temperature is -40°C~85°C TA. D-Typeis the type of this D latch. In FPGA terms, D flip flop is a type of 74AUCseries FPGA. You should not exceed 275MHzin the output frequency of the device. A total of 1elements are contained within it. This process consumes 10μA quiescents. A total of 5 terminations have been made. It is powered from a supply voltage of 1.2V. JK flip flop input capacitance is 2.5pF farads. In terms of electronic devices, this device belongs to the AUCfamily of devices. The design is based on 1bits. 2.7Vis the maximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be above 0.8V.
SN74AUC1G80YEAR Features
Tape & Reel (TR) package
74AUC series
1 Bits
SN74AUC1G80YEAR Applications
There are a lot of Rochester Electronics, LLC SN74AUC1G80YEAR Flip Flops applications.
- Pattern generators
- Balanced Propagation Delays
- Convert a momentary switch to a toggle switch
- Count Modes
- Synchronous counter
- Instrumentation
- Set-reset capability
- Differential Individual
- Asynchronous counter
- Frequency Divider circuits