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74ACT16823DLR

4.5V~5.5V 90MHz 18 Bit D-Type Flip Flop DUAL 74ACT16823 56 Pins 74ACT Series 56-BSSOP (0.295, 7.50mm Width)


  • Manufacturer: Texas Instruments
  • Origchip NO: 815-74ACT16823DLR
  • Package: 56-BSSOP (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 921
  • Description: 4.5V~5.5V 90MHz 18 Bit D-Type Flip Flop DUAL 74ACT16823 56 Pins 74ACT Series 56-BSSOP (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Clock Frequency 90MHz
Propagation Delay 12.9 ns
Quiescent Current 8μA
Turn On Delay Time 7.5 ns
Family ACT
Logic Function D-Type, Flip-Flop
Current - Output High, Low 24mA 24mA
Number of Bits per Element 9
Max Propagation Delay @ V, Max CL 11.5ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 3pF
Power Supply Current-Max (ICC) 0.08mA
Number of Output Lines 3
Count Direction UNIDIRECTIONAL
Clock Edge Trigger Type Positive Edge
Translation N/A
Height 2.79mm
Length 18.41mm
Width 7.49mm
Thickness 2.59mm
Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Lead Free
Factory Lead Time 6 Weeks
Lifecycle Status ACTIVE (Last Updated: 5 days ago)
Contact Plating Gold
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 56-BSSOP (0.295, 7.50mm Width)
Number of Pins 56
Weight 694.790113mg
Operating Temperature -40°C~85°C TA
Packaging Cut Tape (CT)
Series 74ACT
JESD-609 Code e4
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 56
Type D-Type
Additional Feature WITH CLEAR AND CLOCK ENABLE
Subcategory Bus Driver/Transceiver
Packing Method TR
Technology CMOS
Voltage - Supply 4.5V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 5V
Base Part Number 74ACT16823
Function Master Reset
Output Type Tri-State, Non-Inverted
Operating Supply Voltage 5V
Number of Elements 2
Polarity Non-Inverting
Power Supplies 5V
Number of Circuits 1
Load Capacitance 50pF
Number of Ports 2
Output Current 24mA
Number of Bits 18

74ACT16823DLR Overview


The item is packaged in 56-BSSOP (0.295, 7.50mm Width)cases. Package Cut Tape (CT)embeds it. It is configured with Tri-State, Non-Invertedas an output. The trigger configured with it uses Positive Edge. Surface Mountis occupied by this electronic component. A supply voltage of 4.5V~5.5V is required for operation. The operating temperature is -40°C~85°C TA. This D latch has the type D-Type. In terms of FPGAs, it belongs to the 74ACT series. It should not exceed 90MHzin its output frequency. A total of 2elements are present in it. A total of 56terminations have been recorded. JK flip flop belongs to 74ACT16823 family. The D flip flop is powered by a voltage of 5V . Its input capacitance is 3pFfarads. Devices in the ACTfamily are electronic devices. There is an electronic part that is mounted in the way of Surface Mount. With its 56pins, it is designed to work with most electronic flip flops. A Positive Edgeclock edge trigger is used in this device. This part is included in Bus Driver/Transceiver. There are 18bits in this flip flop. Its flexibility is enhanced by 1 circuits. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. A total of 5V power supplies are needed to run it. The D flip flop has no ports embedded. High efficiency requires the supply voltage to be maintained at 5V. With an output current of 24mA, this device offers maximum design flexibility. It is designed with 3 output lines. In terms of quiescent current, it consumes 8μA . In addition, you can refer to the additinal WITH CLEAR AND CLOCK ENABLE of the D latch.

74ACT16823DLR Features


Cut Tape (CT) package
74ACT series
56 pins
18 Bits
5V power supplies

74ACT16823DLR Applications


There are a lot of Texas Instruments 74ACT16823DLR Flip Flops applications.

  • Functionally equivalent to the MC10/100EL29
  • Guaranteed simultaneous switching noise level
  • QML qualified product
  • Test & Measurement
  • Pattern generators
  • Storage registers
  • Supports Live Insertion
  • Cold spare funcion
  • 2 – Bit synchronous counter
  • Shift registers