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  • 74ACT534SC

74ACT534SC

4.5V~5.5V 100MHz D-Type Flip Flop DUAL 40μA 74ACT Series 20-SOIC (0.295, 7.50mm Width)


  • Manufacturer: Rochester Electronics, LLC
  • Origchip NO: 699-74ACT534SC
  • Package: 20-SOIC (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 859
  • Description: 4.5V~5.5V 100MHz D-Type Flip Flop DUAL 40μA 74ACT Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-SOIC (0.295, 7.50mm Width)
Surface Mount YES
Operating Temperature -40°C~85°C TA
Packaging Tube
Series 74ACT
JESD-609 Code e3
Pbfree Code yes
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish MATTE TIN
Technology CMOS
Voltage - Supply 4.5V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 5V
Reach Compliance Code unknown
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
JESD-30 Code R-PDSO-G20
Function Standard
Qualification Status COMMERCIAL
Output Type Tri-State, Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Supply Voltage-Min (Vsup) 4.5V
Number of Ports 2
Clock Frequency 100MHz
Family ACT
Current - Quiescent (Iq) 40μA
Output Characteristics 3-STATE
Current - Output High, Low 24mA 24mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 11.5ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4.5pF
Height Seated (Max) 2.65mm
Width 7.5mm
RoHS Status ROHS3 Compliant

74ACT534SC Overview


In the form of 20-SOIC (0.295, 7.50mm Width), it has been packaged. It is contained within the Tubepackage. As configured, the output uses Tri-State, Inverted. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A 4.5V~5.5Vsupply voltage is required for it to operate. -40°C~85°C TAis the operating temperature. D-Typeis the type of this D latch. JK flip flop belongs to the 74ACTseries of FPGAs. You should not exceed 100MHzin the output frequency of the device. D latch consists of 1 elements. T flip flop consumes 40μA quiescent energy. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The power supply voltage is 5V. This JK flip flop has a 4.5pFfarad input capacitance. ACTis the family of this D flip flop. It reaches the maximum supply voltage (Vsup) at 5.5V. For normal operation, the supply voltage (Vsup) should be kept above 4.5V. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.

74ACT534SC Features


Tube package
74ACT series

74ACT534SC Applications


There are a lot of Rochester Electronics, LLC 74ACT534SC Flip Flops applications.

  • EMI reduction circuitry
  • Dynamic threshold performance
  • Single Up Count-Control Line
  • Circuit Design
  • Computing
  • Count Modes
  • Cold spare funcion
  • Data transfer
  • High Performance Logic for test systems
  • ESD performance