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74ACTQ273MTCX

4.5V~5.5V 189MHz D-Type Flip Flop 74ACTQ273 40μA 74ACTQ Series 20-TSSOP (0.173, 4.40mm Width)


  • Manufacturer: ON Semiconductor
  • Origchip NO: 598-74ACTQ273MTCX
  • Package: 20-TSSOP (0.173, 4.40mm Width)
  • Datasheet: PDF
  • Stock: 463
  • Description: 4.5V~5.5V 189MHz D-Type Flip Flop 74ACTQ273 40μA 74ACTQ Series 20-TSSOP (0.173, 4.40mm Width)(Kg)

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Details

Tags

Parameters
Series 74ACTQ
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 4.5V~5.5V
Base Part Number 74ACTQ273
Function Master Reset
Output Type Non-Inverted
Number of Elements 1
Clock Frequency 189MHz
Current - Quiescent (Iq) 40μA
Current - Output High, Low 24mA 24mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 8.5ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4.5pF
Mounting Type Surface Mount
Package / Case 20-TSSOP (0.173, 4.40mm Width)
Supplier Device Package 20-TSSOP
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)

74ACTQ273MTCX Overview


The package is in the form of 20-TSSOP (0.173, 4.40mm Width). D flip flop is embedded in the Tape & Reel (TR) package. The output it is configured with uses Non-Inverted. The trigger configured with it uses Positive Edge. Surface Mountis positioned in the way of this electronic part. A supply voltage of 4.5V~5.5V is required for operation. The operating temperature is -40°C~85°C TA. This D latch has the type D-Type. JK flip flop belongs to the 74ACTQseries of FPGAs. In order for it to function properly, its output frequency should not exceed 189MHz. The element count is 1 . This process consumes 40μA quiescents. The object belongs to the 74ACTQ273 family. The input capacitance of this JK flip flopis 4.5pF farads.

74ACTQ273MTCX Features


Tape & Reel (TR) package
74ACTQ series

74ACTQ273MTCX Applications


There are a lot of ON Semiconductor 74ACTQ273MTCX Flip Flops applications.

  • Test & Measurement
  • Pattern generators
  • Memory
  • Power down protection
  • QML qualified product
  • Guaranteed simultaneous switching noise level
  • Divide a clock signal by 2 or 4
  • Differential Individual
  • Latch-up performance
  • Data transfer