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  • 74ALVCH16821DGGS

74ALVCH16821DGGS

2.3V~2.7V 3V~3.6V 350MHz D-Type Flip Flop DUAL 56 Pins 74ALVCH Series 56-TFSOP (0.240, 6.10mm Width)


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74ALVCH16821DGGS
  • Package: 56-TFSOP (0.240, 6.10mm Width)
  • Datasheet: PDF
  • Stock: 274
  • Description: 2.3V~2.7V 3V~3.6V 350MHz D-Type Flip Flop DUAL 56 Pins 74ALVCH Series 56-TFSOP (0.240, 6.10mm Width)(Kg)

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Details

Tags

Parameters
Operating Temperature -40°C~85°C TA
Packaging Tube
Series 74ALVCH
JESD-609 Code e4
Part Status Active
Moisture Sensitivity Level (MSL) 2 (1 Year)
Number of Terminations 56
Type D-Type
Additional Feature CAN ALSO OPERATE AT VOLTAGE 3-3.6
Technology CMOS
Voltage - Supply 2.3V~2.7V 3V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Supply Voltage 2.5V
Terminal Pitch 0.5mm
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 2
Polarity Non-Inverting
Number of Ports 2
Clock Frequency 350MHz
Propagation Delay 4.5 ns
Quiescent Current 40μA
Family ALVC/VCX/A
Output Characteristics 3-STATE
Current - Output High, Low 24mA 24mA
Number of Bits per Element 10
Max Propagation Delay @ V, Max CL 4.5ns @ 3.3V, 50pF
Trigger Type Positive Edge
Input Capacitance 5pF
Clock Edge Trigger Type Positive Edge
Length 14mm
Width 6.1mm
RoHS Status ROHS3 Compliant
Factory Lead Time 8 Weeks
Contact Plating Gold
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 56-TFSOP (0.240, 6.10mm Width)
Number of Pins 56

74ALVCH16821DGGS Overview


The flip flop is packaged in 56-TFSOP (0.240, 6.10mm Width). The package Tubecontains it. The output it is configured with uses Tri-State, Non-Inverted. This trigger uses the value Positive Edge. There is an electronic component mounted in the way of Surface Mount. With a supply voltage of 2.3V~2.7V 3V~3.6V volts, it operates. Temperature is set to -40°C~85°C TA. The type of this D latch is D-Type. This type of FPGA is a part of the 74ALVCH series. It should not exceed 350MHzin its output frequency. In total, there are 2 elements. It has been determined that there have been 56 terminations. An input voltage of 2.5Vpowers the D latch. This JK flip flop has a 5pFfarad input capacitance. Devices in the ALVC/VCX/Afamily are electronic devices. This electronic part is mounted in the way of Surface Mount. As you can see from the design, it has pins with 56. There is a clock edge trigger type of Positive Edgeon this device. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. As a result, it consumes 40μA of quiescent current without being affected by external factors. In addition, you can refer to the additinal CAN ALSO OPERATE AT VOLTAGE 3-3.6 of the D latch.

74ALVCH16821DGGS Features


Tube package
74ALVCH series
56 pins

74ALVCH16821DGGS Applications


There are a lot of Nexperia USA Inc. 74ALVCH16821DGGS Flip Flops applications.

  • Count Modes
  • ATE
  • Matched Rise and Fall
  • Supports Live Insertion
  • Reduced system switching noise
  • Latch
  • Storage registers
  • ESCC
  • Buffered Clock
  • Bounce elimination switch