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  • 74AUP1G74GF,115

74AUP1G74GF,115

0.8V~3.6V 315MHz 1 Bit D-Type Flip Flop DUAL 74AUP1G74 8 Pins 74AUP Series 8-XFDFN


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74AUP1G74GF,115
  • Package: 8-XFDFN
  • Datasheet: PDF
  • Stock: 980
  • Description: 0.8V~3.6V 315MHz 1 Bit D-Type Flip Flop DUAL 74AUP1G74 8 Pins 74AUP Series 8-XFDFN(Kg)

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Details

Tags

Parameters
Factory Lead Time 13 Weeks
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-XFDFN
Number of Pins 8
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Series 74AUP
JESD-609 Code e3
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type D-Type
Terminal Finish Tin (Sn)
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Terminal Form NO LEAD
Peak Reflow Temperature (Cel) NOT SPECIFIED
Supply Voltage 1.1V
Terminal Pitch 0.35mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Base Part Number 74AUP1G74
Function Set(Preset) and Reset
Output Type Differential
Number of Elements 1
Polarity Non-Inverting
Supply Voltage-Max (Vsup) 3.6V
Number of Bits 1
Clock Frequency 315MHz
Propagation Delay 14.2 ns
Quiescent Current 500nA
Turn On Delay Time 2.2 ns
Family AUP/ULP/V
Logic Function AND, D-Type
Current - Output High, Low 4mA 4mA
Max Propagation Delay @ V, Max CL 5.8ns @ 3.3V, 30pF
Trigger Type Positive Edge
Input Capacitance 0.6pF
Clock Edge Trigger Type Positive Edge
Height Seated (Max) 0.5mm
RoHS Status ROHS3 Compliant
Lead Free Lead Free

74AUP1G74GF,115 Overview


8-XFDFNis the way it is packaged. As part of the package Tape & Reel (TR), it is embedded. As configured, the output uses Differential. It is configured with the trigger Positive Edge. It is mounted in the way of Surface Mount. A voltage of 0.8V~3.6Vis used as the supply voltage. -40°C~125°C TAis the operating temperature. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. There should be no greater frequency than 315MHzon its output. The list contains 1 elements. It has been determined that there have been 8 terminations. Members of the 74AUP1G74family make up this object. A voltage of 1.1V is used as the power supply for this D latch. Its input capacitance is 0.6pF farads. AUP/ULP/Vis the family of this D flip flop. It is mounted by the way of Surface Mount. As you can see from the design, it has pins with 8. In this device, the clock edge trigger type is Positive Edge. An electronic part designed with 1bits is used in this application. Vsup reaches 3.6V, the maximal supply voltage. In terms of quiescent current, it consumes 500nA .

74AUP1G74GF,115 Features


Tape & Reel (TR) package
74AUP series
8 pins
1 Bits

74AUP1G74GF,115 Applications


There are a lot of Nexperia USA Inc. 74AUP1G74GF,115 Flip Flops applications.

  • Guaranteed simultaneous switching noise level
  • QML qualified product
  • Consumer
  • Pattern generators
  • Individual Asynchronous Resets
  • Test & Measurement
  • Computing
  • Control circuits
  • Balanced 24 mA output drivers
  • Count Modes