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74AUP1G80GW,125

0.8V~3.6V 309MHz 1 Bit D-Type Flip Flop DUAL 74AUP1G80 5 Pins 500nA 74AUP Series 5-TSSOP, SC-70-5, SOT-353

Manufacturer: Nexperia USA Inc.
Origchip NO: 554-74AUP1G80GW,125
Package: 5-TSSOP, SC-70-5, SOT-353
Datasheet: PDF
Stock: 542
Description: 0.8V~3.6V 309MHz 1 Bit D-Type Flip Flop DUAL 74AUP1G80 5 Pins 500nA 74AUP Series 5-TSSOP, SC-70-5, SOT-353(Kg)

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Parameters
Polarity	Inverting
Supply Voltage-Max (Vsup)	3.6V
Supply Voltage-Min (Vsup)	0.8V
Number of Circuits	1
Output Current	20mA
Number of Bits	1
Clock Frequency	309MHz
Propagation Delay	20.7 ns
Turn On Delay Time	2.2 ns
Family	AUP/ULP/V
Current - Quiescent (Iq)	500nA
Current - Output High, Low	4mA 4mA
Max Propagation Delay @ V, Max CL	6.4ns @ 3.3V, 30pF
Trigger Type	Positive Edge
Input Capacitance	1.5pF
Clock Edge Trigger Type	Positive Edge
Radiation Hardening	No
REACH SVHC	No SVHC
RoHS Status	ROHS3 Compliant
Factory Lead Time	4 Weeks
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	5-TSSOP, SC-70-5, SOT-353
Number of Pins	5
Operating Temperature	-40°C~125°C TA
Packaging	Tape & Reel (TR)
Series	74AUP
JESD-609 Code	e3
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	5
Type	D-Type
Terminal Finish	Tin (Sn)
Technology	CMOS
Voltage - Supply	0.8V~3.6V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	1.2V
Time@Peak Reflow Temperature-Max (s)	30
Base Part Number	74AUP1G80
Function	Standard
Output Type	Inverted

74AUP1G80GW,125 Overview

As a result, it is packaged as 5-TSSOP, SC-70-5, SOT-353. The package Tape & Reel (TR)contains it. It is configured with Invertedas an output. Positive Edgeis the trigger it is configured with. Surface Mountis occupied by this electronic component. A 0.8V~3.6Vsupply voltage is required for it to operate. In this case, the operating temperature is -40°C~125°C TA. It belongs to the type D-Typeof flip flops. JK flip flop is a part of the 74AUPseries of FPGAs. A frequency of 309MHzshould be the maximum output frequency. It consumes 500nA of quiescent current without being affected by external factors. In 5terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. Members of the 74AUP1G80family make up this object. The power source is powered by 1.2V. Its input capacitance is 1.5pF farads. AUP/ULP/Vis the family of this D flip flop. There is an electronic part that is mounted in the way of Surface Mount. There are 5pins on it. A Positive Edgeclock edge trigger is used in this device. The flip flop is designed with 1bits. It reaches the maximum supply voltage (Vsup) at 3.6V. A normal operating voltage (Vsup) should remain above 0.8V. 1 circuits are used to achieve its superior flexibility. This T flip flop features a maximum design flexibility due to its output current of 20mA.

74AUP1G80GW,125 Features

Tape & Reel (TR) package
74AUP series
5 pins
1 Bits

74AUP1G80GW,125 Applications

There are a lot of Nexperia USA Inc. 74AUP1G80GW,125 Flip Flops applications.

Shift Registers
Parallel data storage
Latch
Computing
Counters
Set-reset capability
Communications
Differential Individual
Patented noise
Memory