All Products

74AUP2G80GF,115

0.8V~3.6V 309MHz D-Type Flip Flop DUAL 74AUP2G80 8 Pins 500nA 74AUP Series 8-XFDFN


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74AUP2G80GF,115
  • Package: 8-XFDFN
  • Datasheet: PDF
  • Stock: 607
  • Description: 0.8V~3.6V 309MHz D-Type Flip Flop DUAL 74AUP2G80 8 Pins 500nA 74AUP Series 8-XFDFN(Kg)

Purchase & Inquiry

Transport

Purchase

You may place an order without registering to Utmel.
We strongly suggest you sign in before purchasing as you can track your order in real time.

Means of Payment

For your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and wire transfer.

RFQ (Request for Quotations)

It is recommended to request for quotations to get the latest prices and inventories about the part.
Our sales will reply to your request by email within 24 hours.

IMPORTANT NOTICE

1. You'll receive an order information email in your inbox. (Please remember to check the spam folder if you didn't hear from us).
2. Since inventories and prices may fluctuate to some extent, the sales manager is going to reconfirm the order and let you know if there are any updates.

Shipping Cost

Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.)
The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

Shipping Method

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

Delivery Time

Once the goods are shipped, estimated delivery time depends on the shipping methods you chose:

FedEx International, 5-7 business days.

The following are some common countries' logistic time.
transport

Details

Tags

Parameters
Factory Lead Time 13 Weeks
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-XFDFN
Number of Pins 8
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Published 2010
Series 74AUP
JESD-609 Code e3
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type D-Type
Terminal Finish Tin (Sn)
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Supply Voltage 1.1V
Terminal Pitch 0.35mm
Base Part Number 74AUP2G80
Function Standard
Output Type Inverted
Number of Elements 2
Polarity Inverting
Supply Voltage-Max (Vsup) 3.6V
Clock Frequency 309MHz
Propagation Delay 27.2 ns
Turn On Delay Time 2.2 ns
Family AUP/ULP/V
Current - Quiescent (Iq) 500nA
Current - Output High, Low 4mA 4mA
Number of Bits per Element 1
Max Propagation Delay @ V, Max CL 6.4ns @ 3.3V, 30pF
Trigger Type Positive Edge
Input Capacitance 0.6pF
Clock Edge Trigger Type Positive Edge
Height Seated (Max) 0.5mm
Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Lead Free

74AUP2G80GF,115 Overview


In the form of 8-XFDFN, it has been packaged. It is contained within the Tape & Reel (TR)package. In the configuration, Invertedis used as the output. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Surface Mount. A voltage of 0.8V~3.6Vis used as the supply voltage. It is operating at -40°C~125°C TA. It is an electronic flip flop with the type D-Type. The 74AUPseries comprises this type of FPGA. A frequency of 309MHzshould not be exceeded by its output. There are 2 elements in it. There is 500nA quiescent consumption. Terminations are 8. The object belongs to the 74AUP2G80 family. A voltage of 1.1V provides power to the D latch. Its input capacitance is 0.6pF farads. This D flip flop belongs to the family of AUP/ULP/V. In this case, the electronic component is mounted in the way of Surface Mount. A total of 8pins are provided on this board. This device's clock edge trigger type is Positive Edge. In this case, the maximum supply voltage (Vsup) reaches 3.6V.

74AUP2G80GF,115 Features


Tape & Reel (TR) package
74AUP series
8 pins

74AUP2G80GF,115 Applications


There are a lot of Nexperia USA Inc. 74AUP2G80GF,115 Flip Flops applications.

  • Automotive
  • Parallel data storage
  • Frequency Divider circuits
  • Consumer
  • Cold spare funcion
  • Memory
  • Shift registers
  • Communications
  • Individual Asynchronous Resets
  • High Performance Logic for test systems