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  • 74AUP2G80GM,125

74AUP2G80GM,125

0.8V~3.6V 309MHz D-Type Flip Flop QUAD 74AUP2G80 8 Pins 74AUP Series 8-XFQFN Exposed Pad


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74AUP2G80GM,125
  • Package: 8-XFQFN Exposed Pad
  • Datasheet: PDF
  • Stock: 218
  • Description: 0.8V~3.6V 309MHz D-Type Flip Flop QUAD 74AUP2G80 8 Pins 74AUP Series 8-XFQFN Exposed Pad(Kg)

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Details

Tags

Parameters
Factory Lead Time 20 Weeks
Contact Plating Gold
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-XFQFN Exposed Pad
Number of Pins 8
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Published 2010
Series 74AUP
JESD-609 Code e4
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type D-Type
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position QUAD
Peak Reflow Temperature (Cel) 260
Supply Voltage 1.2V
Terminal Pitch 0.5mm
Time@Peak Reflow Temperature-Max (s) 40
Base Part Number 74AUP2G80
Function Standard
Output Type Inverted
Polarity Inverting
Supply Voltage-Max (Vsup) 3.6V
Number of Circuits 2
Clock Frequency 309MHz
Propagation Delay 20.7 ns
Quiescent Current 500nA
Turn On Delay Time 2.2 ns
Family AUP/ULP/V
Logic Function D-Type, Flip-Flop
Current - Output High, Low 4mA 4mA
Number of Bits per Element 1
Max Propagation Delay @ V, Max CL 6.4ns @ 3.3V, 30pF
Trigger Type Positive Edge
Input Capacitance 0.6pF
Number of Output Lines 1
Clock Edge Trigger Type Positive Edge
Height Seated (Max) 0.5mm
Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Lead Free

74AUP2G80GM,125 Overview


8-XFQFN Exposed Padis the way it is packaged. Package Tape & Reel (TR)embeds it. Invertedis the output configured for it. It is configured with a trigger that uses Positive Edge. Surface Mountis in the way of this electric part. Powered by a 0.8V~3.6Vvolt supply, it operates as follows. Temperature is set to -40°C~125°C TA. The type of this D latch is D-Type. JK flip flop belongs to the 74AUPseries of FPGAs. Its output frequency should not exceed 309MHz. Currently, there are 8 terminations. Members of the 74AUP2G80family make up this object. A voltage of 1.2V is used as the power supply for this D latch. Its input capacitance is 0.6pFfarads. In terms of electronic devices, this device belongs to the AUP/ULP/Vfamily of devices. There is an electronic part that is mounted in the way of Surface Mount. This board is designed with 8pins on it. In this device, the clock edge trigger type is Positive Edge. Vsup reaches its maximum value at 3.6V. 2 circuits are used to achieve its superior flexibility. The JK flip flop is with 1 output lines to operate. It consumes a total of 500nA quiescent current at any given time.

74AUP2G80GM,125 Features


Tape & Reel (TR) package
74AUP series
8 pins

74AUP2G80GM,125 Applications


There are a lot of Nexperia USA Inc. 74AUP2G80GM,125 Flip Flops applications.

  • Counters
  • Differential Individual
  • CMOS Process
  • Data transfer
  • Instrumentation
  • Common Clocks
  • Asynchronous counter
  • Patented noise
  • Computing
  • Individual Asynchronous Resets