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  • 74F112SJ

74F112SJ

4.5V~5.5V 105MHz JK Type Flip Flop DUAL 19mA 74F Series 16-SOIC (0.209, 5.30mm Width)


  • Manufacturer: Rochester Electronics, LLC
  • Origchip NO: 699-74F112SJ
  • Package: 16-SOIC (0.209, 5.30mm Width)
  • Datasheet: PDF
  • Stock: 572
  • Description: 4.5V~5.5V 105MHz JK Type Flip Flop DUAL 19mA 74F Series 16-SOIC (0.209, 5.30mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 16-SOIC (0.209, 5.30mm Width)
Surface Mount YES
Operating Temperature 0°C~70°C TA
Packaging Tube
Series 74F
JESD-609 Code e3
Pbfree Code yes
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 16
Type JK Type
Terminal Finish MATTE TIN
Technology TTL
Voltage - Supply 4.5V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 5V
Reach Compliance Code unknown
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Function Set(Preset) and Reset
Qualification Status Not Qualified
Output Type Differential
Number of Elements 2
Supply Voltage-Max (Vsup) 5.5V
Supply Voltage-Min (Vsup) 4.5V
Clock Frequency 105MHz
Family F/FAST
Current - Quiescent (Iq) 19mA
Current - Output High, Low 1mA 20mA
Output Polarity COMPLEMENTARY
Number of Bits per Element 1
Max Propagation Delay @ V, Max CL 6.5ns @ 5V, 50pF
Trigger Type Negative Edge
Propagation Delay (tpd) 7.5 ns
fmax-Min 80 MHz
Width 5.3mm
RoHS Status ROHS3 Compliant

74F112SJ Overview


The flip flop is packaged in 16-SOIC (0.209, 5.30mm Width). Package Tubeembeds it. It is configured with Differentialas an output. Negative Edgeis the trigger it is configured with. It is mounted in the way of Surface Mount. With a supply voltage of 4.5V~5.5V volts, it operates. In the operating environment, the temperature is 0°C~70°C TA. This D latch has the type JK Type. In FPGA terms, D flip flop is a type of 74Fseries FPGA. It should not exceed 105MHzin its output frequency. In total, it contains 2 elements. T flip flop consumes 19mA quiescent energy. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The power source is powered by 5V. F/FASTis the family of this D flip flop. As soon as 5.5Vis reached, Vsup reaches its maximum value. For normal operation, the supply voltage (Vsup) should be above 4.5V.

74F112SJ Features


Tube package
74F series

74F112SJ Applications


There are a lot of Rochester Electronics, LLC 74F112SJ Flip Flops applications.

  • Divide a clock signal by 2 or 4
  • Single Up Count-Control Line
  • Event Detectors
  • Memory
  • Convert a momentary switch to a toggle switch
  • Pattern generators
  • Control circuits
  • Bounce elimination switch
  • Differential Individual
  • Buffer registers