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  • 74LV273D,112

74LV273D,112

1V~5.5V 100MHz D-Type Flip Flop DUAL 74LV273 160μA 74LV Series 20-SOIC (0.295, 7.50mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV273D,112
  • Package: 20-SOIC (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 901
  • Description: 1V~5.5V 100MHz D-Type Flip Flop DUAL 74LV273 160μA 74LV Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-SOIC (0.295, 7.50mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 1998
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV273
JESD-30 Code R-PDSO-G20
Function Master Reset
Qualification Status Not Qualified
Output Type Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Clock Frequency 100MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 160μA
Current - Output High, Low 12mA 12mA
Output Polarity TRUE
Max I(ol) 0.006 A
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 19ns @ 5V, 50pF
Prop. Delay@Nom-Sup 24 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 24 ns
fmax-Min 20 MHz
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 2.65mm
Width 7.5mm
RoHS Status ROHS3 Compliant

74LV273D,112 Overview


The package is in the form of 20-SOIC (0.295, 7.50mm Width). It is included in the package Tube. T flip flop uses Non-Invertedas its output configuration. It is configured with a trigger that uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. A 1V~5.5Vsupply voltage is required for it to operate. In this case, the operating temperature is -40°C~125°C TA. This D latch has the type D-Type. It belongs to the 74LVseries of FPGAs. This D flip flop should not have a frequency greater than 100MHz. A total of 1elements are present in it. During its operation, it consumes 160μA quiescent energy. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The object belongs to the 74LV273 family. An input voltage of 3.3Vpowers the D latch. There is 3.5pF input capacitance for this T flip flop. It is a member of the LV/LV-A/LVX/Hfamily of D flip flop. There is a FF/Latchesbase part number assigned to the RS flip flops. Vsup reaches 5.5V, the maximal supply voltage. Normally, the supply voltage (Vsup) should be above 1V. A power supply of 3.3Vis required to operate it.

74LV273D,112 Features


Tube package
74LV series
3.3V power supplies

74LV273D,112 Applications


There are a lot of NXP USA Inc. 74LV273D,112 Flip Flops applications.

  • Safety Clamp
  • Guaranteed simultaneous switching noise level
  • Circuit Design
  • Supports Live Insertion
  • Balanced Propagation Delays
  • Computers
  • Latch
  • Buffer registers
  • Count Modes
  • Balanced 24 mA output drivers