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  • 74LV273DB,112

74LV273DB,112

1V~5.5V 100MHz D-Type Flip Flop DUAL 74LV273 160μA 74LV Series 20-SSOP (0.209, 5.30mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV273DB,112
  • Package: 20-SSOP (0.209, 5.30mm Width)
  • Datasheet: PDF
  • Stock: 788
  • Description: 1V~5.5V 100MHz D-Type Flip Flop DUAL 74LV273 160μA 74LV Series 20-SSOP (0.209, 5.30mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-SSOP (0.209, 5.30mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 1998
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV273
JESD-30 Code R-PDSO-G20
Function Master Reset
Qualification Status Not Qualified
Output Type Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Clock Frequency 100MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 160μA
Current - Output High, Low 12mA 12mA
Output Polarity TRUE
Max I(ol) 0.006 A
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 19ns @ 5V, 50pF
Prop. Delay@Nom-Sup 24 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 24 ns
fmax-Min 20 MHz
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 2mm
Length 7.2mm
Width 5.3mm
RoHS Status ROHS3 Compliant

74LV273DB,112 Overview


The item is packaged in 20-SSOP (0.209, 5.30mm Width)cases. The package Tubecontains it. Non-Invertedis the output configured for it. This trigger uses the value Positive Edge. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates at 1V~5.5Vvolts. A temperature of -40°C~125°C TAis used in the operation. It belongs to the type D-Typeof flip flops. In terms of FPGAs, it belongs to the 74LV series. It should not exceed 100MHzin terms of its output frequency. D latch consists of 1 elements. During its operation, it consumes 160μA quiescent energy. There are 20 terminations,D latch belongs to the 74LV273 family. The D flip flop is powered by a voltage of 3.3V . Input capacitance of this device is 3.5pF farads. LV/LV-A/LVX/His the family of this D flip flop. There is a FF/Latchesbase part number assigned to the RS flip flops. The maximal supply voltage (Vsup) reaches 5.5V. Keeping the supply voltage (Vsup) above 1V is necessary for normal operation. It runs on 3.3Vvolts of power.

74LV273DB,112 Features


Tube package
74LV series
3.3V power supplies

74LV273DB,112 Applications


There are a lot of NXP USA Inc. 74LV273DB,112 Flip Flops applications.

  • Computers
  • High Performance Logic for test systems
  • Shift Registers
  • ESD protection
  • Buffered Clock
  • CMOS Process
  • 2 – Bit synchronous counter
  • ESCC
  • Latch
  • Matched Rise and Fall