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  • 74LV273N,112

74LV273N,112

1V~5.5V 100MHz D-Type Flip Flop DUAL 74LV273 160μA 74LV Series 20-DIP (0.300, 7.62mm)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV273N,112
  • Package: 20-DIP (0.300, 7.62mm)
  • Datasheet: PDF
  • Stock: 503
  • Description: 1V~5.5V 100MHz D-Type Flip Flop DUAL 74LV273 160μA 74LV Series 20-DIP (0.300, 7.62mm)(Kg)

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Details

Tags

Parameters
Mounting Type Through Hole
Package / Case 20-DIP (0.300, 7.62mm)
Surface Mount NO
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 1998
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 2.54mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV273
JESD-30 Code R-PDIP-T20
Function Master Reset
Qualification Status Not Qualified
Output Type Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Clock Frequency 100MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 160μA
Current - Output High, Low 12mA 12mA
Output Polarity TRUE
Max I(ol) 0.006 A
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 16ns @ 5V, 50pF
Prop. Delay@Nom-Sup 24 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 24 ns
fmax-Min 20 MHz
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 4.2mm
Length 26.73mm
Width 7.62mm
RoHS Status ROHS3 Compliant

74LV273N,112 Overview


The package is in the form of 20-DIP (0.300, 7.62mm). The package Tubecontains it. There is a Non-Invertedoutput configured with it. It is configured with a trigger that uses a value of Positive Edge. There is an electrical part that is mounted in the way of Through Hole. A 1V~5.5Vsupply voltage is required for it to operate. It is operating at a temperature of -40°C~125°C TA. The type of this D latch is D-Type. JK flip flop is a part of the 74LVseries of FPGAs. You should not exceed 100MHzin the output frequency of the device. D latch consists of 1 elements. As a result, it consumes 160μA of quiescent current without being affected by external factors. There have been 20 terminations. D latch belongs to the 74LV273 family. It is powered from a supply voltage of 3.3V. A 3.5pFfarad input capacitance is provided by this T flip flop. Electronic devices of this type belong to the LV/LV-A/LVX/Hfamily. There is a base part number FF/Latchesfor the RS flip flops. In this case, the maximum supply voltage (Vsup) reaches 5.5V. Keeping the supply voltage (Vsup) above 1V is necessary for normal operation. A total of 3.3V power supplies are needed to run it.

74LV273N,112 Features


Tube package
74LV series
3.3V power supplies

74LV273N,112 Applications


There are a lot of NXP USA Inc. 74LV273N,112 Flip Flops applications.

  • Circuit Design
  • ESD protection
  • Supports Live Insertion
  • Frequency Divider circuits
  • Buffer registers
  • ESCC
  • Frequency Dividers
  • Asynchronous counter
  • Data Synchronizers
  • Instrumentation