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  • 74LV374PW,112

74LV374PW,112

1V~5.5V 77MHz D-Type Flip Flop DUAL 74LV374 160μA 74LV Series 20-TSSOP (0.173, 4.40mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV374PW,112
  • Package: 20-TSSOP (0.173, 4.40mm Width)
  • Datasheet: PDF
  • Stock: 770
  • Description: 1V~5.5V 77MHz D-Type Flip Flop DUAL 74LV374 160μA 74LV Series 20-TSSOP (0.173, 4.40mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-TSSOP (0.173, 4.40mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 2009
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Reach Compliance Code unknown
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV374
JESD-30 Code R-PDSO-G20
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 77MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 160μA
Output Characteristics 3-STATE
Current - Output High, Low 16mA 16mA
Output Polarity TRUE
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 19ns @ 5V, 50pF
Prop. Delay@Nom-Sup 29 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 36 ns
Max Frequency@Nom-Sup 20000000Hz
Length 6.5mm
Width 4.4mm
RoHS Status ROHS3 Compliant

74LV374PW,112 Overview


In the form of 20-TSSOP (0.173, 4.40mm Width), it has been packaged. You can find it in the Tubepackage. It is configured with Tri-State, Non-Invertedas an output. In the configuration of the trigger, Positive Edgeis used. There is an electronic component mounted in the way of Surface Mount. The supply voltage is set to 1V~5.5V. It is operating at -40°C~125°C TA. This D latch has the type D-Type. JK flip flop is a part of the 74LVseries of FPGAs. A frequency of 77MHzshould be the maximum output frequency. A total of 1elements are present in it. As a result, it consumes 160μA quiescent current. A total of 20 terminations have been made. The 74LV374 family contains it. A voltage of 3.3V is used to power it. There is 3.5pF input capacitance for this T flip flop. In terms of electronic devices, this device belongs to the LV/LV-A/LVX/Hfamily of devices. This device has the base part number FF/Latches. As soon as 3.6Vis reached, Vsup reaches its maximum value. A normal operating voltage (Vsup) should remain above 1V. An electrical current of 3.3V volts is applied to it. The D flip flop has no ports embedded.

74LV374PW,112 Features


Tube package
74LV series
3.3V power supplies

74LV374PW,112 Applications


There are a lot of NXP USA Inc. 74LV374PW,112 Flip Flops applications.

  • Buffer registers
  • Frequency division
  • ESCC
  • Storage registers
  • Computers
  • Pattern generators
  • Common Clocks
  • Data storage
  • Patented noise
  • Convert a momentary switch to a toggle switch