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  • 74LV377D,112

74LV377D,112

1V~3.6V 70MHz D-Type Flip Flop DUAL 74LV377 20μA 74LV Series 20-SOIC (0.295, 7.50mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LV377D,112
  • Package: 20-SOIC (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 938
  • Description: 1V~3.6V 70MHz D-Type Flip Flop DUAL 74LV377 20μA 74LV Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-SOIC (0.295, 7.50mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tube
Published 1998
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Additional Feature WITH HOLD MODE
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV377
JESD-30 Code R-PDSO-G20
Function Standard
Qualification Status Not Qualified
Output Type Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Clock Frequency 70MHz
Family LV/LV-A/LVX/H
Current - Quiescent (Iq) 20μA
Current - Output High, Low 6mA 6mA
Output Polarity TRUE
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 30ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup 36 ns
Trigger Type Positive Edge
Input Capacitance 3.5pF
Propagation Delay (tpd) 36 ns
fmax-Min 20 MHz
Max Frequency@Nom-Sup 20000000Hz
Height Seated (Max) 2.65mm
Width 7.5mm
RoHS Status ROHS3 Compliant

74LV377D,112 Overview


In the form of 20-SOIC (0.295, 7.50mm Width), it has been packaged. It is included in the package Tube. T flip flop uses Non-Invertedas its output configuration. The trigger it is configured with uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. It operates with a supply voltage of 1V~3.6V. A temperature of -40°C~125°C TAis used in the operation. Logic flip flops of this type are classified as D-Type. JK flip flop is a part of the 74LVseries of FPGAs. This D flip flop should not have a frequency greater than 70MHz. D latch consists of 1 elements. As a result, it consumes 20μA quiescent current. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. If you search by 74LV377, you will find similar parts. The power source is powered by 3.3V. Its input capacitance is 3.5pFfarads. Electronic devices of this type belong to the LV/LV-A/LVX/Hfamily. The RS flip flops belongs to FF/Latches base part number. Vsup reaches its maximum value at 5.5V. Normal operation requires a supply voltage (Vsup) above 1V. The power supply is 3.3V. Furthermore, it has WITH HOLD MODEas a characteristic.

74LV377D,112 Features


Tube package
74LV series
3.3V power supplies

74LV377D,112 Applications


There are a lot of NXP USA Inc. 74LV377D,112 Flip Flops applications.

  • Common Clocks
  • Reduced system switching noise
  • Event Detectors
  • QML qualified product
  • Differential Individual
  • Safety Clamp
  • Supports Live Insertion
  • Registers
  • EMI reduction circuitry
  • Shift Registers