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  • 74LVC1G74GT,115

74LVC1G74GT,115

1.65V~5.5V 200MHz 1 Bit D-Type Flip Flop DUAL 74LVC1G74 8 Pins 40μA 74LVC Series 8-XFDFN


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74LVC1G74GT,115
  • Package: 8-XFDFN
  • Datasheet: PDF
  • Stock: 837
  • Description: 1.65V~5.5V 200MHz 1 Bit D-Type Flip Flop DUAL 74LVC1G74 8 Pins 40μA 74LVC Series 8-XFDFN(Kg)

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Details

Tags

Parameters
Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Lead Free
Factory Lead Time 13 Weeks
Contact Plating Tin
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-XFDFN
Number of Pins 8
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Published 2010
Series 74LVC
JESD-609 Code e3
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type D-Type
Technology CMOS
Voltage - Supply 1.65V~5.5V
Terminal Position DUAL
Peak Reflow Temperature (Cel) 260
Supply Voltage 1.8V
Terminal Pitch 0.5mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LVC1G74
Function Set(Preset) and Reset
Output Type Differential
Polarity Non-Inverting
Number of Circuits 1
Number of Bits 1
Clock Frequency 200MHz
Propagation Delay 4.1 ns
Quiescent Current 100nA
Turn On Delay Time 2.5 ns
Family LVC/LCX/Z
Logic Function AND, D-Type, Flip-Flop
Current - Quiescent (Iq) 40μA
Current - Output High, Low 32mA 32mA
Max Propagation Delay @ V, Max CL 4.1ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4pF
Number of Input Lines 4
Number of Output Lines 2
Max Supply Voltage (DC) 5.5V
Clock Edge Trigger Type Positive Edge
Height Seated (Max) 0.5mm

74LVC1G74GT,115 Overview


It is packaged in the way of 8-XFDFN. The package Tape & Reel (TR)contains it. Currently, the output is configured to use Differential. It is configured with the trigger Positive Edge. This electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of 1.65V~5.5V. The operating temperature is -40°C~125°C TA. This D latch has the type D-Type. The 74LVCseries comprises this type of FPGA. It should not exceed 200MHzin its output frequency. There is a consumption of 40μAof quiescent energy. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. It is a member of the 74LVC1G74 family. A voltage of 1.8V provides power to the D latch. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. An electronic device belonging to the family LVC/LCX/Zcan be found here. It is mounted by the way of Surface Mount. There are 8pins on it. The clock edge trigger type for this device is Positive Edge. An electronic part designed with 1bits is used in this application. 1 circuits are used to achieve its superior flexibility. To operate, the chip has a total of 2 output lines. A total of 4input lines have been provided. It consumes 100nA current.

74LVC1G74GT,115 Features


Tape & Reel (TR) package
74LVC series
8 pins
1 Bits

74LVC1G74GT,115 Applications


There are a lot of Nexperia USA Inc. 74LVC1G74GT,115 Flip Flops applications.

  • Convert a momentary switch to a toggle switch
  • Set-reset capability
  • Latch-up performance
  • Bus hold
  • Balanced 24 mA output drivers
  • Computers
  • Data Synchronizers
  • Balanced Propagation Delays
  • Frequency Divider circuits
  • Latch