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  • 74LVC1G80GS,132

74LVC1G80GS,132

1.65V~5.5V 400MHz 1 Bit D-Type Flip Flop DUAL 74LVC1G80 6 Pins 200μA 74LVC Series 6-XFDFN


  • Manufacturer: Nexperia USA Inc.
  • Origchip NO: 554-74LVC1G80GS,132
  • Package: 6-XFDFN
  • Datasheet: PDF
  • Stock: 353
  • Description: 1.65V~5.5V 400MHz 1 Bit D-Type Flip Flop DUAL 74LVC1G80 6 Pins 200μA 74LVC Series 6-XFDFN(Kg)

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Details

Tags

Parameters
Factory Lead Time 13 Weeks
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 6-XFDFN
Number of Pins 6
Operating Temperature -40°C~125°C TA
Packaging Tape & Reel (TR)
Published 2010
Series 74LVC
JESD-609 Code e3
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 6
Type D-Type
Terminal Finish Tin (Sn)
Max Power Dissipation 250mW
Technology CMOS
Voltage - Supply 1.65V~5.5V
Terminal Position DUAL
Terminal Form NO LEAD
Supply Voltage 3.3V
Terminal Pitch 0.35mm
Base Part Number 74LVC1G80
Function Standard
Output Type Inverted
Number of Elements 1
Polarity Inverting
Supply Voltage-Max (Vsup) 5.5V
Number of Bits 1
Clock Frequency 400MHz
Propagation Delay 13 ns
Turn On Delay Time 1.8 ns
Family LVC/LCX/Z
Current - Quiescent (Iq) 200μA
Current - Output High, Low 32mA 32mA
Max Propagation Delay @ V, Max CL 4.5ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 5pF
fmax-Min 200 MHz
Clock Edge Trigger Type Positive Edge
Height Seated (Max) 0.35mm
RoHS Status ROHS3 Compliant

74LVC1G80GS,132 Overview


It is embeded in 6-XFDFN case. You can find it in the Tape & Reel (TR)package. T flip flop uses Invertedas the output. The trigger it is configured with uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates with an input voltage of 1.65V~5.5V volts. In the operating environment, the temperature is -40°C~125°C TA. D-Typeis the type of this D latch. JK flip flop belongs to the 74LVCseries of FPGAs. There should be no greater frequency than 400MHzon its output. In total, it contains 1 elements. It consumes 200μA of quiescent current without being affected by external factors. In 6terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The object belongs to the 74LVC1G80 family. An input voltage of 3.3Vpowers the D latch. The input capacitance of this JK flip flopis 5pF farads. This D flip flop belongs to the family of LVC/LCX/Z. There is an electronic part mounted in the way of Surface Mount. The 6pins are designed into the board. This device's clock edge trigger type is Positive Edge. 1bits are used in its design. 5.5Vis the maximum supply voltage (Vsup).

74LVC1G80GS,132 Features


Tape & Reel (TR) package
74LVC series
6 pins
1 Bits

74LVC1G80GS,132 Applications


There are a lot of Nexperia USA Inc. 74LVC1G80GS,132 Flip Flops applications.

  • Storage registers
  • Count Modes
  • Dynamic threshold performance
  • Individual Asynchronous Resets
  • Clock pulse
  • Shift registers
  • Instrumentation
  • Test & Measurement
  • Memory
  • ESCC