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74LVC821AD,112

1.65V~3.6V 200MHz D-Type Flip Flop DUAL 74LVC821 10μA 74LVC Series 24-SOIC (0.295, 7.50mm Width)

Manufacturer: NXP USA Inc.
Origchip NO: 568-74LVC821AD,112
Package: 24-SOIC (0.295, 7.50mm Width)
Datasheet: PDF
Stock: 167
Description: 1.65V~3.6V 200MHz D-Type Flip Flop DUAL 74LVC821 10μA 74LVC Series 24-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type	Surface Mount
Package / Case	24-SOIC (0.295, 7.50mm Width)
Surface Mount	YES
Operating Temperature	-40°C~125°C TA
Packaging	Tube
Series	74LVC
JESD-609 Code	e4
Part Status	Obsolete
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	24
Type	D-Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latches
Technology	CMOS
Voltage - Supply	1.65V~3.6V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	2.7V
Time@Peak Reflow Temperature-Max (s)	30
Base Part Number	74LVC821
JESD-30 Code	R-PDSO-G24
Function	Standard
Qualification Status	Not Qualified
Output Type	Tri-State, Non-Inverted
Number of Elements	1
Supply Voltage-Max (Vsup)	3.6V
Power Supplies	3.3V
Load Capacitance	50pF
Number of Ports	2
Clock Frequency	200MHz
Family	LVC/LCX/Z
Current - Quiescent (Iq)	10μA
Output Characteristics	3-STATE
Current - Output High, Low	24mA 24mA
Output Polarity	TRUE
Max I(ol)	0.024 A
Number of Bits per Element	10
Max Propagation Delay @ V, Max CL	7.3ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup	9.5 ns
Trigger Type	Positive Edge
Input Capacitance	5pF
Height Seated (Max)	2.65mm
Width	7.5mm
RoHS Status	ROHS3 Compliant

74LVC821AD,112 Overview

The flip flop is packaged in 24-SOIC (0.295, 7.50mm Width). D flip flop is included in the Tubepackage. T flip flop uses Tri-State, Non-Invertedas the output. The trigger it is configured with uses Positive Edge. Surface Mountis occupied by this electronic component. A voltage of 1.65V~3.6Vis used as the supply voltage. A temperature of -40°C~125°C TAis considered to be the operating temperature. This logic flip flop is classified as type D-Type. In terms of FPGAs, it belongs to the 74LVC series. Its output frequency should not exceed 200MHz Hz. The list contains 1 elements. As a result, it consumes 10μA of quiescent current without being affected by external factors. There are 24 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The object belongs to the 74LVC821 family. A voltage of 2.7V is used to power it. Its input capacitance is 5pFfarads. This D flip flop belongs to the family of LVC/LCX/Z. It is part of the FF/Latchesbase part number family. As soon as 3.6Vis reached, Vsup reaches its maximum value. A total of 3.3V power supplies are needed to run it. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.

74LVC821AD,112 Features

Tube package
74LVC series
3.3V power supplies

74LVC821AD,112 Applications

There are a lot of NXP USA Inc. 74LVC821AD,112 Flip Flops applications.

ATE
Communications
Set-reset capability
Pattern generators
Matched Rise and Fall
Clock pulse
Common Clocks
QML qualified product
Storage Registers
Divide a clock signal by 2 or 4