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  • 74LVC821APW,112

74LVC821APW,112

1.65V~3.6V 200MHz D-Type Flip Flop DUAL 74LVC821 10μA 74LVC Series 24-TSSOP (0.173, 4.40mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LVC821APW,112
  • Package: 24-TSSOP (0.173, 4.40mm Width)
  • Datasheet: PDF
  • Stock: 559
  • Description: 1.65V~3.6V 200MHz D-Type Flip Flop DUAL 74LVC821 10μA 74LVC Series 24-TSSOP (0.173, 4.40mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 24-TSSOP (0.173, 4.40mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tube
Series 74LVC
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 24
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1.65V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 2.7V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LVC821
JESD-30 Code R-PDSO-G24
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 200MHz
Family LVC/LCX/Z
Current - Quiescent (Iq) 10μA
Output Characteristics 3-STATE
Current - Output High, Low 24mA 24mA
Output Polarity TRUE
Max I(ol) 0.024 A
Number of Bits per Element 10
Max Propagation Delay @ V, Max CL 7.3ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup 9.5 ns
Trigger Type Positive Edge
Input Capacitance 5pF
Length 7.8mm
Width 4.4mm
RoHS Status ROHS3 Compliant

74LVC821APW,112 Overview


As a result, it is packaged as 24-TSSOP (0.173, 4.40mm Width). It is included in the package Tube. The output it is configured with uses Tri-State, Non-Inverted. There is a trigger configured with Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A 1.65V~3.6Vsupply voltage is required for it to operate. In the operating environment, the temperature is -40°C~125°C TA. D-Typedescribes this flip flop. In this case, it is a type of FPGA belonging to the 74LVC series. It should not exceed 200MHzin its output frequency. D latch consists of 1 elements. As a result, it consumes 10μA of quiescent current without being affected by external factors. It has been determined that there have been 24 terminations. The object belongs to the 74LVC821 family. The power supply voltage is 2.7V. Input capacitance of this device is 5pF farads. This D flip flop belongs to the family of LVC/LCX/Z. There is a FF/Latchesbase part number assigned to the RS flip flops. The maximal supply voltage (Vsup) reaches 3.6V. A total of 3.3V power supplies are needed to run it. There are 2 ports embedded in the flip flops.

74LVC821APW,112 Features


Tube package
74LVC series
3.3V power supplies

74LVC821APW,112 Applications


There are a lot of NXP USA Inc. 74LVC821APW,112 Flip Flops applications.

  • ESCC
  • Shift Registers
  • Clock pulse
  • Automotive
  • ATE
  • Buffered Clock
  • Divide a clock signal by 2 or 4
  • Pattern generators
  • Instrumentation
  • Single Up Count-Control Line