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74LVCH16374APAG8

2.7V~3.6V 150MHz D-Type Flip Flop 74LVCH16374 10μA 74LVCH Series 48-TFSOP (0.240, 6.10mm Width)


  • Manufacturer: Renesas Electronics America Inc.
  • Origchip NO: 668-74LVCH16374APAG8
  • Package: 48-TFSOP (0.240, 6.10mm Width)
  • Datasheet: PDF
  • Stock: 976
  • Description: 2.7V~3.6V 150MHz D-Type Flip Flop 74LVCH16374 10μA 74LVCH Series 48-TFSOP (0.240, 6.10mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time 12 Weeks
Mounting Type Surface Mount
Package / Case 48-TFSOP (0.240, 6.10mm Width)
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 74LVCH
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 2.7V~3.6V
Base Part Number 74LVCH16374
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 2
Clock Frequency 150MHz
Current - Quiescent (Iq) 10μA
Current - Output High, Low 24mA 24mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 4.5ns @ 3.3V, 50pF
Trigger Type Positive Edge
Input Capacitance 4.5pF
RoHS Status ROHS3 Compliant

74LVCH16374APAG8 Overview


The flip flop is packaged in a case of 48-TFSOP (0.240, 6.10mm Width). D flip flop is included in the Tape & Reel (TR)package. T flip flop is configured with an output of Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. It is mounted in the way of Surface Mount. Powered by a 2.7V~3.6Vvolt supply, it operates as follows. Temperature is set to -40°C~85°C TA. D-Typeis the type of this D latch. In FPGA terms, D flip flop is a type of 74LVCHseries FPGA. You should not exceed 150MHzin its output frequency. The list contains 2 elements. Despite external influences, it consumes 10μAof quiescent current. This D latch belongs to the family of 74LVCH16374. Its input capacitance is 4.5pF farads.

74LVCH16374APAG8 Features


Tape & Reel (TR) package
74LVCH series

74LVCH16374APAG8 Applications


There are a lot of Renesas Electronics America Inc. 74LVCH16374APAG8 Flip Flops applications.

  • Consumer
  • Divide a clock signal by 2 or 4
  • Buffer registers
  • Common Clocks
  • Data transfer
  • Shift registers
  • Single Down Count-Control Line
  • High Performance Logic for test systems
  • Safety Clamp
  • Computing