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  • 74LVT374DB,112

74LVT374DB,112

2.7V~3.6V 200MHz D-Type Flip Flop DUAL 74LVT374 190μA 74LVT Series 20-SSOP (0.209, 5.30mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-74LVT374DB,112
  • Package: 20-SSOP (0.209, 5.30mm Width)
  • Datasheet: PDF
  • Stock: 639
  • Description: 2.7V~3.6V 200MHz D-Type Flip Flop DUAL 74LVT374 190μA 74LVT Series 20-SSOP (0.209, 5.30mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-SSOP (0.209, 5.30mm Width)
Surface Mount YES
Operating Temperature -40°C~85°C TA
Packaging Tube
Series 74LVT
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Subcategory FF/Latches
Technology BICMOS
Voltage - Supply 2.7V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LVT374
JESD-30 Code R-PDSO-G20
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 2.7V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 200MHz
Family LVT
Current - Quiescent (Iq) 190μA
Output Characteristics 3-STATE
Current - Output High, Low 32mA 64mA
Output Polarity TRUE
Max I(ol) 0.064 A
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 5.2ns @ 3.3V, 50pF
Trigger Type Positive Edge
Input Capacitance 4pF
Propagation Delay (tpd) 5.5 ns
Height Seated (Max) 2mm
Length 7.2mm
Width 5.3mm
RoHS Status ROHS3 Compliant

74LVT374DB,112 Overview


It is embeded in 20-SSOP (0.209, 5.30mm Width) case. It is contained within the Tubepackage. It is configured with Tri-State, Non-Invertedas an output. It is configured with a trigger that uses a value of Positive Edge. There is an electric part mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. Currently, the operating temperature is -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. FPGAs belonging to the 74LVTseries contain this type of chip. A frequency of 200MHzshould be the maximum output frequency. A total of 1 elements are present. T flip flop consumes 190μA quiescent energy. Currently, there are 20 terminations. This D latch belongs to the family of 74LVT374. An input voltage of 3.3Vpowers the D latch. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. In this case, the D flip flop belongs to the LVTfamily. There is a base part number FF/Latchesfor the RS flip flops. It reaches the maximum supply voltage (Vsup) at 3.6V. Normally, the supply voltage (Vsup) should be kept above 2.7V. In order for the device to operate, it requires 3.3V power supplies. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.

74LVT374DB,112 Features


Tube package
74LVT series
3.3V power supplies

74LVT374DB,112 Applications


There are a lot of NXP USA Inc. 74LVT374DB,112 Flip Flops applications.

  • Data Synchronizers
  • Differential Individual
  • Modulo – n – counter
  • Counters
  • Common Clocks
  • Single Down Count-Control Line
  • EMI reduction circuitry
  • Functionally equivalent to the MC10/100EL29
  • Balanced 24 mA output drivers
  • Parallel data storage