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74LVT74D,118
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The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Clock Frequency | 345MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 1mA |
| Current - Output High, Low | 20mA 32mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5 ns |
| Length | 8.65mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74LVT74D,118 Overview
The item is packaged in 14-SOIC (0.154, 3.90mm Width)cases. It is contained within the Tape & Reel (TR)package. This output is configured with Differential. This trigger uses the value Positive Edge. This electronic part is mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. In this case, the operating temperature is -40°C~85°C TA. This electronic flip flop is of type D-Type. JK flip flop is a part of the 74LVTseries of FPGAs. It should not exceed 345MHzin its output frequency. The element count is 2 . It consumes 1mA of quiescent Terminations are 14. D latch belongs to the 74LVT74 family. A voltage of 3.3V provides power to the D latch. There is 3pF input capacitance for this T flip flop. It is a member of the LVTfamily of D flip flop. This device is part of the FF/Latchesbase part number family. In this case, the maximum supply voltage (Vsup) reaches 3.6V. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TAPE AND REEL. The D latch operates on 3.3V volts.
74LVT74D,118 Features
Tape & Reel (TR) package
74LVT series
3.3V power supplies
74LVT74D,118 Applications
There are a lot of NXP USA Inc. 74LVT74D,118 Flip Flops applications.
- Pattern generators
- CMOS Process
- Individual Asynchronous Resets
- Registers
- Set-reset capability
- Cold spare funcion
- High Performance Logic for test systems
- Patented noise
- Digital electronics systems
- Computing