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DM74ALS374WMX
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Shipping Cost
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Currently, our products are shipped through DHL, FedEx, SF, and UPS.
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FedEx International, 5-7 business days.
The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ALS |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 35MHz |
| Family | ALS |
| Current - Quiescent (Iq) | 19mA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 2.6mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 16ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
DM74ALS374WMX Overview
The flip flop is packaged in 20-SOIC (0.295, 7.50mm Width). D flip flop is embedded in the Tape & Reel (TR) package. T flip flop is configured with an output of Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. Surface Mountis occupied by this electronic component. A voltage of 4.5V~5.5Vis used as the supply voltage. 0°C~70°C TAis the operating temperature. There is D-Type type of electronic flip flop associated with this device. This type of FPGA is a part of the 74ALS series. Its output frequency should not exceed 35MHz. D latch consists of 1 elements. During its operation, it consumes 19mA quiescent energy. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The D flip flop is powered by a voltage of 5V . Devices in the ALSfamily are electronic devices. There is a 5.5Vmaximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be kept above 4.5V. The D flip flop is embedded with 2ports.
DM74ALS374WMX Features
Tape & Reel (TR) package
74ALS series
DM74ALS374WMX Applications
There are a lot of Rochester Electronics, LLC DM74ALS374WMX Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Parallel data storage
- Latch-up performance
- ESD protection
- Power down protection
- Reduced system switching noise
- Computing
- Latch
- Shift Registers
- Divide a clock signal by 2 or 4