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  • EPM7064LC68-15

EPM7064LC68-15

1.27mm PMIC 68 Pin 100MHz 5V PLCC


  • Manufacturer: Altera
  • Origchip NO: 2936-EPM7064LC68-15
  • Package: PLCC
  • Datasheet: PDF
  • Stock: 551
  • Description: 1.27mm PMIC 68 Pin 100MHz 5V PLCC (Kg)

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Details

Tags

Parameters
Factory Lead Time 41 Weeks
Mount Surface Mount
Package / Case PLCC
Number of Pins 68
Published 1998
JESD-609 Code e0
Pbfree Code no
Part Status Discontinued
Moisture Sensitivity Level (MSL) 2
Number of Terminations 68
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature 70°C
Min Operating Temperature 0°C
Additional Feature CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form J BEND
Peak Reflow Temperature (Cel) 220
Supply Voltage 5V
Terminal Pitch 1.27mm
Frequency 100MHz
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 68
Operating Supply Voltage 5V
Temperature Grade COMMERCIAL
Max Supply Voltage 5.25V
Min Supply Voltage 4.75V
Number of I/O 52
Memory Type EEPROM
Propagation Delay 15 ns
Turn On Delay Time 15 ns
Frequency (Max) 151.5MHz
Programmable Logic Type EE PLD
Number of Gates 1250
Number of Programmable I/O 52
Number of Logic Blocks (LABs) 4
Speed Grade 15
Output Function MACROCELL
Number of Macro Cells 64
JTAG BST NO
In-System Programmable NO
Height 3.81mm
Length 24.23mm
Width 24.23mm
Radiation Hardening No
RoHS Status RoHS Compliant
Lead Free Contains Lead

EPM7064LC68-15 Overview


There are 64 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).You can find it in package [0].In this case, there are 52 I/Os programmed.The termination of a device is set to [0].QUADis the terminal position of this electrical part.There is 5V voltage supply for this device.It belongs to the family [0].It is equipped with 68 pin count.It is also characterized by CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V.In digital circuits, there are 1250gates, which act as a basic building block.Optimal efficiency requires a supply voltage of [0].Data storage is performed using [0].In this case, Surface Mountis used to mount the electronic component.68pins are included in its design.This device operates at a voltage of 5.25Vas its maximum supply voltage.With a minimal supply voltage of [0], it operates.Programmable I/Os are counted up 52.It is possible to achieve a frequency of 100MHz.The operating temperature should be higher than 0°C.The operating temperature should be lower than 70°C.Its basic building block is composed of 4 logic blocks (LABs).The maximum frequency should not exceed 151.5MHz.Programmable logic types can be divided into EE PLD.

EPM7064LC68-15 Features


PLCC package
52 I/Os
68 pin count
68 pins
4 logic blocks (LABs)

EPM7064LC68-15 Applications


There are a lot of Altera EPM7064LC68-15 CPLDs applications.

  • Configurable Addressing of I/O Boards
  • Custom shift registers
  • Wide Vin Industrial low power SMPS
  • I/O expansion
  • Interface bridging
  • Digital multiplexers
  • Power automation
  • Portable digital devices
  • Address decoding
  • Digital designs