All Products

EPM7192SQC160-7F

3.3/55V 0.65mm PMIC 160 Pin 5V PQFP


  • Manufacturer: Altera
  • Origchip NO: 2936-EPM7192SQC160-7F
  • Package: PQFP
  • Datasheet: PDF
  • Stock: 423
  • Description: 3.3/55V 0.65mm PMIC 160 Pin 5V PQFP (Kg)

Purchase & Inquiry

Transport

Purchase

You may place an order without registering to Utmel.
We strongly suggest you sign in before purchasing as you can track your order in real time.

Means of Payment

For your convenience, we accept multiple payment methods in USD, including PayPal, Credit Card, and wire transfer.

RFQ (Request for Quotations)

It is recommended to request for quotations to get the latest prices and inventories about the part.
Our sales will reply to your request by email within 24 hours.

IMPORTANT NOTICE

1. You'll receive an order information email in your inbox. (Please remember to check the spam folder if you didn't hear from us).
2. Since inventories and prices may fluctuate to some extent, the sales manager is going to reconfirm the order and let you know if there are any updates.

Shipping Cost

Shipping starts at $40, but some countries will exceed $40. For example (South Africa, Brazil, India, Pakistan, Israel, etc.)
The basic freight (for package ≤0.5kg or corresponding volume) depends on the time zone and country.

Shipping Method

Currently, our products are shipped through DHL, FedEx, SF, and UPS.

Delivery Time

Once the goods are shipped, estimated delivery time depends on the shipping methods you chose:

FedEx International, 5-7 business days.

The following are some common countries' logistic time.
transport

Details

Tags

Parameters
Mount Surface Mount
Package / Case PQFP
Number of Pins 160
Packaging Bulk
Published 1998
JESD-609 Code e0
Pbfree Code no
Part Status Discontinued
Moisture Sensitivity Level (MSL) 3
Number of Terminations 160
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature 70°C
Min Operating Temperature 0°C
Additional Feature YES
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 245
Supply Voltage 5V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Pin Count 160
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 5.25V
Power Supplies 3.3/55V
Temperature Grade COMMERCIAL
Supply Voltage-Min (Vsup) 4.75V
Number of I/O 124
Clock Frequency 166.7MHz
Propagation Delay 7.5 ns
Programmable Logic Type EE PLD
Number of Gates 3750
Number of Logic Blocks (LABs) 12
Output Function MACROCELL
Number of Macro Cells 192
JTAG BST YES
In-System Programmable YES
Height Seated (Max) 4.07mm
Length 28mm
Width 28mm
RoHS Status RoHS Compliant
Lead Free Contains Lead

EPM7192SQC160-7F Overview


In the mobile phone network, there are 192macro cells, which are cells with high-power antennas and towers.The item is packaged with PQFP.It is programmed with 124 I/Os.It is programmed to terminate devices at [0].This electrical part has a terminal position of QUADand is connected to the ground.An electrical supply voltage of 5V is used to power it.This part is in the family [0].It is recommended to package the chip by Bulk.It has 160pins programmed.This device is also capable of displaying [0].In digital circuits, there are 3750gates, which act as a basic building block.Surface Mountis the mounting point of this electronic part.The device has a pinout of [0].This device runs on 3.3/55Vvolts of electricity.A maximum supply voltage (Vsup) of 5.25V is provided.There should be a temperature above 0°Cat the time of operation.Ideally, the operating temperature should be below 70°C.Its basic building block is composed of 12 logic blocks (LABs).Voltage supply (Vsup) should be higher than 4.75V.It should not exceed 166.7MHzin terms of clockfrequency.It is possible to classify programmable logic as EE PLD.

EPM7192SQC160-7F Features


PQFP package
124 I/Os
160 pin count
160 pins
3.3/55V power supplies
12 logic blocks (LABs)

EPM7192SQC160-7F Applications


There are a lot of Altera EPM7192SQC160-7F CPLDs applications.

  • Address decoding
  • Multiple Clock Source Selection
  • State machine design
  • Boolean function generators
  • Interface bridging
  • Software-Driven Hardware Configuration
  • Software-driven hardware configuration
  • ToR/Aggregation/Core Switch and Router
  • Battery operated portable devices
  • SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management