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  • EPM7256SRC208-15

EPM7256SRC208-15

0.5mm PMIC 208 Pin 100MHz 5V PQFP


  • Manufacturer: Altera
  • Origchip NO: 2936-EPM7256SRC208-15
  • Package: PQFP
  • Datasheet: PDF
  • Stock: 583
  • Description: 0.5mm PMIC 208 Pin 100MHz 5V PQFP (Kg)

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Details

Tags

Parameters
Turn On Delay Time 15 ns
Frequency (Max) 128.2MHz
Programmable Logic Type EE PLD
Number of Gates 5000
Number of Programmable I/O 164
Number of Logic Blocks (LABs) 16
Speed Grade 15
Output Function MACROCELL
Number of Macro Cells 256
JTAG BST YES
In-System Programmable YES
Height Seated (Max) 4.1mm
Length 28mm
Width 28mm
Radiation Hardening No
RoHS Status RoHS Compliant
Lead Free Contains Lead
Mount Surface Mount
Package / Case PQFP
Number of Pins 208
Published 1998
JESD-609 Code e0
Pbfree Code no
Part Status Discontinued
Moisture Sensitivity Level (MSL) 3
Number of Terminations 208
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature 70°C
Min Operating Temperature 0°C
Additional Feature CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 220
Supply Voltage 5V
Terminal Pitch 0.5mm
Frequency 100MHz
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 208
Operating Supply Voltage 5V
Temperature Grade COMMERCIAL
Max Supply Voltage 5.25V
Min Supply Voltage 4.75V
Number of I/O 164
Memory Type EEPROM
Propagation Delay 15 ns

EPM7256SRC208-15 Overview


The mobile phone network has 256 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).The item is enclosed in a PQFP package.The device has 164inputs and outputs.208terminations are programmed into the device.Its terminal position is QUAD.A voltage of 5V is used as the power supply for this device.It belongs to the family [0].208pins are programmed on the chip.When using this device, CONFIGURABLE I/O OPERATION WITH 3.3V OR 5Vcan also be found.It is possible to construct digital circuits using 5000gates, which are devices that serve as building blocks.If high efficiency is to be achieved, the supply voltage should be maintained at [0].It is adopted to store data in [0].It is mounted by Surface Mount.There are 208pins on it.With a maximum supply voltage of [0], it operates.It operates with the minimal supply voltage of 4.75V.There are a total of 164 Programmable I/Os.This frequency can be achieved at 100MHz.Ideally, the operating temperature should be greater than 0°C.It is recommended that the operating temperature be below 70°C.There are 16 logic blocks (LABs) in its basic building block.It is recommended that the maximum frequency be less than 128.2MHz.This kind of FPGA is composed of EE PLD.

EPM7256SRC208-15 Features


PQFP package
164 I/Os
208 pin count
208 pins
16 logic blocks (LABs)

EPM7256SRC208-15 Applications


There are a lot of Altera EPM7256SRC208-15 CPLDs applications.

  • Synchronous or asynchronous mode
  • Power Meter SMPS
  • Code converters
  • Field programmable gate
  • SUPERVISORY FUNCTION (LVD AND WATCHDOG)
  • Wireless Infrastructure Base Band Unit and Remote Radio Unit
  • SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
  • ToR/Aggregation/Core Switch and Router
  • Address decoding
  • I2C BUS INTERFACE