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M5LV-256/68-12YNC

0.65mm PMIC 100 Pin 3.3V PQFP

Manufacturer: Lattice Semiconductor
Origchip NO: 477-M5LV-256/68-12YNC
Package: PQFP
Datasheet: -
Stock: 842
Description: 0.65mm PMIC 100 Pin 3.3V PQFP (Kg)

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Details

Tags

Parameters
Mount	Surface Mount
Package / Case	PQFP
Number of Pins	100
JESD-609 Code	e3
Pbfree Code	yes
Moisture Sensitivity Level (MSL)	3
Number of Terminations	100
ECCN Code	EAR99
Terminal Finish	Matte Tin (Sn)
Max Operating Temperature	70°C
Min Operating Temperature	0°C
HTS Code	8542.39.00.01
Technology	CMOS
Terminal Position	QUAD
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	245
Supply Voltage	3.3V
Terminal Pitch	0.65mm
Time@Peak Reflow Temperature-Max (s)	40
Pin Count	100
Operating Supply Voltage	3.3V
Temperature Grade	COMMERCIAL
Max Supply Voltage	3.6V
Min Supply Voltage	3V
Number of I/O	68
Clock Frequency	71.4MHz
Propagation Delay	12 ns
Turn On Delay Time	12 ns
Organization	0 DEDICATED INPUTS, 68 I/O
Programmable Logic Type	EE PLD
Output Function	MACROCELL
Height Seated (Max)	3.4mm
Length	20mm
Width	14mm
Radiation Hardening	No
RoHS Status	RoHS Compliant

M5LV-256/68-12YNC Overview

It is part of the PQFP package.The device is programmed with 68 I/Os.There is a 100terminations set on devices.This electrical component has a terminal position of 0.It is powered by a voltage of 3.3V volts.There are 100 pins on the chip.The supply voltage should be maintained at 3.3V for high efficiency.The electronic component is mounted by Surface Mount.There are 100 pins on the device.It operates with the maximal supply voltage of 3.6V.With a minimal supply voltage of [0], it operates.It is recommended that the operating temperature be greater than 0°C.Ideally, the operating temperature should be below 70°C.The clock frequency of the device should not exceed 71.4MHz.It is possible to classify programmable logic as EE PLD.

M5LV-256/68-12YNC Features

PQFP package
68 I/Os
100 pin count
100 pins

M5LV-256/68-12YNC Applications

There are a lot of Lattice Semiconductor M5LV-256/68-12YNC CPLDs applications.

TIMERS/COUNTERS
Power Meter SMPS
Interface bridging
ROM patching
D/T registers and latches
SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
ToR/Aggregation/Core Switch and Router
Reset swapping
State machine design
Power up sequencing