MC100EP35D

MC100EP35D Overview

It is embeded in 8-SOIC (0.154, 3.90mm Width) case. The Tubepackage contains it. T flip flop uses Differentialas its output configuration. The trigger it is configured with uses Positive Edge. There is an electric part mounted in the way of Surface Mount. A voltage of -3V~-5.5Vis used as the supply voltage. -40°C~85°C TAis the operating temperature. Logic flip flops of this type are classified as JK Type. In this case, it is a type of FPGA belonging to the 100EP series. There should be no greater frequency than 3GHzon its output. Terminations are 8. You can search similar parts based on 100EP35. A voltage of 3.3V is used as the power supply for this D latch. Surface Mount mounts this electronic component. Basically, it is designed with a set of 8 pins. This device's clock edge trigger type is Positive Edge. It is included in FF/Latches. The flip flop is designed with 2bits. It reaches the maximum supply voltage (Vsup) at 5.5V. The supply voltage (Vsup) should be kept above 3V for normal operation. On the basis of its reliable performance, this D flip flop is well suited for use with RAIL. In order for the device to operate, it requires -4.5V power supplies. In order to operate, the chip has 1 output lines. NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5Vis also one of its characteristics. -50mA is set as the high level output current. There is 50mA output current at the low level.

MC100EP35D Features

Tube package
100EP series
8 pins
2 Bits
-4.5V power supplies

MC100EP35D Applications

There are a lot of ON Semiconductor MC100EP35D Flip Flops applications.

• Frequency division
• Modulo – n – counter
• Set-reset capability
• ESCC
• Common Clocks
• Safety Clamp
• Data transfer
• ESD protection
• Balanced Propagation Delays
• Computers