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  • MC100EP35DR2G

MC100EP35DR2G

-3V~-5.5V 3GHz 2 Bit JK Type Flip Flop DUAL 50mA 100EP Series 8-SOIC (0.154, 3.90mm Width)


  • Manufacturer: Rochester Electronics, LLC
  • Origchip NO: 699-MC100EP35DR2G
  • Package: 8-SOIC (0.154, 3.90mm Width)
  • Datasheet: PDF
  • Stock: 733
  • Description: -3V~-5.5V 3GHz 2 Bit JK Type Flip Flop DUAL 50mA 100EP Series 8-SOIC (0.154, 3.90mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 8-SOIC (0.154, 3.90mm Width)
Surface Mount YES
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 100EP
JESD-609 Code e3
Pbfree Code no
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type JK Type
Terminal Finish MATTE TIN
Additional Feature NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
Technology ECL
Voltage - Supply -3V~-5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Time@Peak Reflow Temperature-Max (s) 40
JESD-30 Code R-PDSO-G8
Function Reset
Qualification Status COMMERCIAL
Output Type Differential
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Supply Voltage-Min (Vsup) 3V
Number of Bits 2
Clock Frequency 3GHz
Current - Quiescent (Iq) 50mA
Output Polarity COMPLEMENTARY
Trigger Type Positive Edge
Propagation Delay (tpd) 0.49 ns
Length 4.9mm
Width 3.9mm
RoHS Status ROHS3 Compliant

MC100EP35DR2G Overview


The package is in the form of 8-SOIC (0.154, 3.90mm Width). You can find it in the Tape & Reel (TR)package. This output is configured with Differential. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. A voltage of -3V~-5.5Vis used as the supply voltage. A temperature of -40°C~85°C TAis considered to be the operating temperature. This D latch has the type JK Type. JK flip flop is a part of the 100EPseries of FPGAs. Its output frequency should not exceed 3GHz Hz. A total of 1 elements are present. It consumes 50mA of quiescent current without being affected by external factors. The number of terminations is 8. The power supply voltage is 3.3V. It is designed with a number of bits of 2. As soon as 5.5Vis reached, Vsup reaches its maximum value. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 3V. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.

MC100EP35DR2G Features


Tape & Reel (TR) package
100EP series
2 Bits

MC100EP35DR2G Applications


There are a lot of Rochester Electronics, LLC MC100EP35DR2G Flip Flops applications.

  • Divide a clock signal by 2 or 4
  • Matched Rise and Fall
  • Safety Clamp
  • Latch
  • Bounce elimination switch
  • Count Modes
  • Registers
  • ESD protection
  • Counters
  • QML qualified product