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MC100LVEL30DWG

-3V~-3.8V 1.2GHz D-Type Flip Flop DUAL 100LVEL30 20 Pins 62mA 100LVEL Series 20-SOIC (0.295, 7.50mm Width)


  • Manufacturer: ON Semiconductor
  • Origchip NO: 598-MC100LVEL30DWG
  • Package: 20-SOIC (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 717
  • Description: -3V~-3.8V 1.2GHz D-Type Flip Flop DUAL 100LVEL30 20 Pins 62mA 100LVEL Series 20-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time 8 Weeks
Lifecycle Status LIFETIME (Last Updated: 4 days ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 20-SOIC (0.295, 7.50mm Width)
Number of Pins 20
Operating Temperature -40°C~85°C TA
Packaging Tube
Published 2006
Series 100LVEL
JESD-609 Code e3
Pbfree Code yes
Part Status Obsolete
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 20
Type D-Type
Terminal Finish Tin (Sn)
Subcategory FF/Latches
Technology ECL
Voltage - Supply -3V~-3.8V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Time@Peak Reflow Temperature-Max (s) 40
Base Part Number 100LVEL30
Function Set(Preset) and Reset
Output Type Differential
Polarity Non-Inverting
Supply Voltage-Min (Vsup) 3V
Number of Circuits 3
Clock Frequency 1.2GHz
Propagation Delay 820 ps
Turn On Delay Time 570 ps
Logic Function AND, D-Type, Flip-Flop
Current - Quiescent (Iq) 62mA
Output Characteristics OPEN-EMITTER
Halogen Free Halogen Free
Number of Bits per Element 1
Trigger Type Positive Edge
Clock Edge Trigger Type Positive Edge
Height 2.4mm
Length 12.95mm
Width 7.6mm
Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Lead Free

MC100LVEL30DWG Overview


It is packaged in the way of 20-SOIC (0.295, 7.50mm Width). The Tubepackage contains it. In the configuration, Differentialis used as the output. It is configured with a trigger that uses a value of Positive Edge. Surface Mountis in the way of this electric part. A voltage of -3V~-3.8Vis required for its operation. -40°C~85°C TAis the operating temperature. D-Typedescribes this flip flop. JK flip flop is a part of the 100LVELseries of FPGAs. There should be no greater frequency than 1.2GHzon its output. There is a consumption of 62mAof quiescent energy. Terminations are 20. The 100LVEL30 family contains this object. It is powered from a supply voltage of 3.3V. A part of the electronic system is mounted in the way of Surface Mount. 20pins are included in its design. This device exhibits a clock edge trigger type of Positive Edge. This part is included in FF/Latches. Normally, the supply voltage (Vsup) should be above 3V. Due to its superior flexibility, it uses 3 circuits.

MC100LVEL30DWG Features


Tube package
100LVEL series
20 pins

MC100LVEL30DWG Applications


There are a lot of ON Semiconductor MC100LVEL30DWG Flip Flops applications.

  • Event Detectors
  • EMI reduction circuitry
  • ESD protection
  • Count Modes
  • Circuit Design
  • Supports Live Insertion
  • Instrumentation
  • Balanced Propagation Delays
  • Data transfer
  • Data storage