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  • MC100LVEL51DG

MC100LVEL51DG

-3V~-3.8V 2.8GHz 1 Bit D-Type Flip Flop DUAL 100LVEL51 8 Pins 35mA 100LVEL Series 8-SOIC (0.154, 3.90mm Width)


  • Manufacturer: ON Semiconductor
  • Origchip NO: 598-MC100LVEL51DG
  • Package: 8-SOIC (0.154, 3.90mm Width)
  • Datasheet: PDF
  • Stock: 569
  • Description: -3V~-3.8V 2.8GHz 1 Bit D-Type Flip Flop DUAL 100LVEL51 8 Pins 35mA 100LVEL Series 8-SOIC (0.154, 3.90mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time 11 Weeks
Lifecycle Status ACTIVE (Last Updated: 4 days ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-SOIC (0.154, 3.90mm Width)
Number of Pins 8
Operating Temperature -40°C~85°C TA
Packaging Tube
Published 2000
Series 100LVEL
JESD-609 Code e3
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Type D-Type
Terminal Finish Tin (Sn)
Subcategory FF/Latches
Packing Method RAIL
Technology ECL
Voltage - Supply -3V~-3.8V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 3.3V
Time@Peak Reflow Temperature-Max (s) 40
Base Part Number 100LVEL51
Function Reset
Output Type Differential
Operating Supply Voltage 3.3V
Polarity Non-Inverting
Supply Voltage-Min (Vsup) 3V
Number of Circuits 1
Output Current 50mA
Number of Bits 1
Clock Frequency 2.8GHz
Propagation Delay 590 ps
Turn On Delay Time 475 ps
Logic Function D-Type, Flip-Flop
Current - Quiescent (Iq) 35mA
Output Characteristics OPEN-EMITTER
Halogen Free Halogen Free
Prop. Delay@Nom-Sup 0.55 ns
Trigger Type Positive, Negative
Power Supply Current-Max (ICC) 37mA
Clock Edge Trigger Type Positive Edge
Max Frequency@Nom-Sup 2900000000Hz
Length 4.9mm
Width 3.9mm
Radiation Hardening No
REACH SVHC No SVHC
RoHS Status ROHS3 Compliant
Lead Free Lead Free

MC100LVEL51DG Overview


As a result, it is packaged as 8-SOIC (0.154, 3.90mm Width). D flip flop is included in the Tubepackage. It is configured with Differentialas an output. This trigger uses the value Positive, Negative. There is an electric part mounted in the way of Surface Mount. It operates with a supply voltage of -3V~-3.8V. A temperature of -40°C~85°C TAis used in the operation. The type of this D latch is D-Type. JK flip flop is a part of the 100LVELseries of FPGAs. It should not exceed 2.8GHzin its output frequency. It consumes 35mA of quiescent current without being affected by external factors. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. JK flip flop belongs to 100LVEL51 family. An input voltage of 3.3Vpowers the D latch. Electronic part Surface Mountis mounted in the way. This board is designed with 8pins on it. A Positive Edgeclock edge trigger is used in this device. This part is included in FF/Latches. There are 1bits in its design. Normally, the supply voltage (Vsup) should be kept above 3V. The superior flexibility is achieved through the use of 1 circuits. As a result of its reliability, this D flip flop is ideally suited for RAIL. The supply voltage should be maintained at 3.3V for high efficiency. With a current output of 50mA , it offers maximum design flexibility.

MC100LVEL51DG Features


Tube package
100LVEL series
8 pins
1 Bits

MC100LVEL51DG Applications


There are a lot of ON Semiconductor MC100LVEL51DG Flip Flops applications.

  • Latch-up performance
  • Frequency division
  • Computing
  • Cold spare funcion
  • Pattern generators
  • Data transfer
  • Balanced 24 mA output drivers
  • Individual Asynchronous Resets
  • Communications
  • Matched Rise and Fall