MC10EP35DTR2G

MC10EP35DTR2G Overview

The package is in the form of 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). There is an embedded version in the package Tape & Reel (TR). T flip flop uses Differentialas its output configuration. In the configuration of the trigger, Positive Edgeis used. It is mounted in the way of Surface Mount. It operates with a supply voltage of -3V~-5.5V. It is operating at -40°C~85°C TA. This D latch has the type JK Type. JK flip flop is a part of the 10EPseries of FPGAs. A frequency of 3GHzshould not be exceeded by its output. In total, it contains 1 elements. There is a consumption of 50mAof quiescent energy. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. An input voltage of 3.3Vpowers the D latch. Devices in the 10Efamily are electronic devices. There are 2bits in this flip flop. As soon as 5.5Vis reached, Vsup reaches its maximum value. A normal operating voltage (Vsup) should remain above 3V. In addition, NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5Vis a characteristic of it.

MC10EP35DTR2G Features

Tape & Reel (TR) package
10EP series
2 Bits

MC10EP35DTR2G Applications

There are a lot of Rochester Electronics, LLC MC10EP35DTR2G Flip Flops applications.

• QML qualified product
• Power down protection
• Frequency Dividers
• Set-reset capability
• Instrumentation
• Latch
• High Performance Logic for test systems
• Frequency Divider circuits
• Dynamic threshold performance
• Parallel data storage