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MC68030RC50C
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The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Package / Case | 128-BPGA |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 2007 |
| Series | M680x0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Base Part Number | MC68030 |
| Speed | 50MHz |
| Core Processor | 68030 |
| Voltage - I/O | 5.0V |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| Additional Interfaces | SCI, SPI |
| RoHS Status | ROHS3 Compliant |
MC68030RC50C Description
The MC68030RC50C is an integrated controller that incorporates the capabilities of the MC68030 integer unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family and the 32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor interface provided with the MC68020 and MC68030.
MC68030RC50C Features
Complete 32-Bit Nonmultiplexed Address and Data Buses
Sixteen 32-Bit General-Purpose Data and Address Registers
Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers
Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection
Pipelined Architecture with Increased Parallelism Allows:
- Internal Caches Accesses in Parallel with Bus Transfers
- Overlapped Instruction Execution
MC68030RC50C Applications
Automotive
Infotainment & cluster
Communications equipment
Datacom module
Industrial
Power delivery