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MPC8377CVRALG

1mm PowerPC e300c4s 11.8/2.52.5/3.3V 32-bit Microprocessor MPC83xx Series MPC8377 1V 689-BBGA Exposed Pad


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-MPC8377CVRALG
  • Package: 689-BBGA Exposed Pad
  • Datasheet: PDF
  • Stock: 178
  • Description: 1mm PowerPC e300c4s 11.8/2.52.5/3.3V 32-bit Microprocessor MPC83xx Series MPC8377 1V 689-BBGA Exposed Pad (Kg)

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Details

Tags

Parameters
Package / Case 689-BBGA Exposed Pad
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tray
Published 2002
Series MPC83xx
JESD-609 Code e2
Part Status Obsolete
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 689
ECCN Code 3A991.A.2
Terminal Finish TIN COPPER/TIN SILVER
HTS Code 8542.31.00.01
Subcategory Microprocessors
Technology CMOS
Terminal Position BOTTOM
Terminal Form BALL
Peak Reflow Temperature (Cel) 260
Supply Voltage 1V
Terminal Pitch 1mm
Time@Peak Reflow Temperature-Max (s) 40
Base Part Number MPC8377
JESD-30 Code S-PBGA-B689
Supply Voltage-Max (Vsup) 1.05V
Power Supplies 11.8/2.52.5/3.3V
Supply Voltage-Min (Vsup) 0.95V
Speed 667MHz
uPs/uCs/Peripheral ICs Type MICROPROCESSOR
Core Processor PowerPC e300c4s
Bit Size 32
Address Bus Width 15
Boundary Scan YES
Low Power Mode YES
External Data Bus Width 64
Format FLOATING POINT
Integrated Cache YES
Voltage - I/O 1.8V 2.5V 3.3V
Ethernet 10/100/1000Mbps (2)
Number of Cores/Bus Width 1 Core 32-Bit
Graphics Acceleration No
RAM Controllers DDR, DDR2
USB USB 2.0 + PHY (1)
Additional Interfaces DUART, I2C, MMC/SD, PCI, SPI
SATA SATA 3Gbps (2)
Height Seated (Max) 2.46mm
Length 31mm
RoHS Status ROHS3 Compliant

MPC8377CVRALG Description

This chip incorporates the e300c4s core, which includes 32 KB of L1 instruction and data caches, and on-chip memory management units (MMUs). The device offers two enhanced three-speed 10, 100, and 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB 2.0 dual-role controller, a programmable interrupt controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip.



MPC8377CVRALG Features

e300c4s core built on Power Architecture? technology with 32 KB instruction cache and 32 KB

data cache, a floating point unit, and two integer units

DDR1/DDR2 memory controller supporting a 32/64-bit interface

Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MT/s operation

32-bit local bus interface running up to 133-MT/s

USB 2.0 (full/high speed) support

Power management controller for low-power consumption

High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration

Optional security engine provides acceleration for control and data plane security protocols