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  • N74F821D,602

N74F821D,602

4.5V~5.5V 180MHz D-Type Flip Flop DUAL 74F821 105mA 74F Series 24-SOIC (0.295, 7.50mm Width)


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-N74F821D,602
  • Package: 24-SOIC (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 973
  • Description: 4.5V~5.5V 180MHz D-Type Flip Flop DUAL 74F821 105mA 74F Series 24-SOIC (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 24-SOIC (0.295, 7.50mm Width)
Surface Mount YES
Operating Temperature 0°C~70°C TA
Packaging Tube
Published 2000
Series 74F
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 24
Type D-Type
Terminal Finish NICKEL PALLADIUM GOLD
Additional Feature POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION
Subcategory FF/Latches
Technology TTL
Voltage - Supply 4.5V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 5V
Reach Compliance Code unknown
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74F821
JESD-30 Code R-PDSO-G24
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 5V
Supply Voltage-Min (Vsup) 4.5V
Load Capacitance 50pF
Number of Ports 2
Clock Frequency 180MHz
Family F/FAST
Current - Quiescent (Iq) 105mA
Output Characteristics 3-STATE
Current - Output High, Low 24mA 64mA
Output Polarity TRUE
Max I(ol) 0.064 A
Number of Bits per Element 10
Max Propagation Delay @ V, Max CL 8.5ns @ 5V, 50pF
Prop. Delay@Nom-Sup 9.5 ns
Trigger Type Positive Edge
Propagation Delay (tpd) 9.5 ns
Height Seated (Max) 2.65mm
Width 7.5mm
RoHS Status ROHS3 Compliant

N74F821D,602 Overview


In the form of 24-SOIC (0.295, 7.50mm Width), it has been packaged. There is an embedded version in the package Tube. Currently, the output is configured to use Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. The electronic part is mounted in the way of Surface Mount. Powered by a 4.5V~5.5Vvolt supply, it operates as follows. Currently, the operating temperature is 0°C~70°C TA. This logic flip flop is classified as type D-Type. JK flip flop belongs to the 74Fseries of FPGAs. It should not exceed 180MHzin its output frequency. D latch consists of 1 elements. As a result, it consumes 105mA quiescent current. A total of 24terminations have been recorded. JK flip flop belongs to 74F821 family. A voltage of 5V provides power to the D latch. In this case, the D flip flop belongs to the F/FASTfamily. The part you are looking for is included in FF/Latches. It reaches the maximum supply voltage (Vsup) at 5.5V. Normally, the supply voltage (Vsup) should be above 4.5V. The D latch operates on 5V volts. This D flip flop is equipped with 0 ports. POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTIONis also one of its characteristics.

N74F821D,602 Features


Tube package
74F series
5V power supplies

N74F821D,602 Applications


There are a lot of NXP USA Inc. N74F821D,602 Flip Flops applications.

  • Bus hold
  • Count Modes
  • Safety Clamp
  • Pattern generators
  • 2 – Bit synchronous counter
  • Divide a clock signal by 2 or 4
  • ATE
  • ESD performance
  • Data storage
  • Data transfer