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  • P2020NXE2MHC

P2020NXE2MHC

1mm PowerPC e500v2 1.05V 32-bit Microprocessor QorIQ P2 Series P2020 1.05V 689-BBGA Exposed Pad


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-P2020NXE2MHC
  • Package: 689-BBGA Exposed Pad
  • Datasheet: PDF
  • Stock: 958
  • Description: 1mm PowerPC e500v2 1.05V 32-bit Microprocessor QorIQ P2 Series P2020 1.05V 689-BBGA Exposed Pad (Kg)

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Details

Tags

Parameters
Factory Lead Time 12 Weeks
Package / Case 689-BBGA Exposed Pad
Surface Mount YES
Operating Temperature -40°C~125°C TA
Packaging Tray
Published 2002
Series QorIQ P2
JESD-609 Code e2
Part Status Active
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 689
ECCN Code 5A002.A.1
Terminal Finish TIN COPPER/TIN SILVER
HTS Code 8542.31.00.01
Subcategory Microprocessors
Technology CMOS
Terminal Position BOTTOM
Terminal Form BALL
Peak Reflow Temperature (Cel) 260
Supply Voltage 1.05V
Terminal Pitch 1mm
Time@Peak Reflow Temperature-Max (s) 40
Base Part Number P2020
JESD-30 Code S-PBGA-B689
Power Supplies 1.05V
Speed 1.2GHz
uPs/uCs/Peripheral ICs Type MICROPROCESSOR
Core Processor PowerPC e500v2
Bit Size 32
Boundary Scan YES
Format FLOATING POINT
Integrated Cache YES
Ethernet 10/100/1000Mbps (3)
Number of Cores/Bus Width 2 Core 32-Bit
Graphics Acceleration No
RAM Controllers DDR2, DDR3
USB USB 2.0 + PHY (2)
Additional Interfaces DUART, I2C, MMC/SD, SPI
Co-Processors/DSP Security; SEC 3.3
Security Features Cryptography, Random Number Generator
Height Seated (Max) 2.46mm
Length 31mm
RoHS Status ROHS3 Compliant


P2020NXE2MHC Description


A link status bit (TBI SR [Link Status]) in the TBI Status Register (SR) represents the current state of the SGMII link. The TBI link status bit should become a b'1 after detecting IDLE sequences if Auto-Negotiation (AN) is disabled, and stay at b'1 as long as valid data is received and the TBI is not reset. After numerous invalid characters are received or the TBI is reset, the TBI link status bit should become a b'0, indicating the link is down. When AN is enabled, the TBI link status bit is not set to b'1 until auto-negotiation is complete (TBI CR [AN DONE]=1), but the same criteria apply as when AN is disabled for the TBI link status bit to be set to b'1.


P2020NXE2MHC Features


? PIC (programmable interrupt controller) that adheres to the OpenPIC standard

? Two DMA controllers with four channels

? Timers, DUART, and two I2C controllers

? A more powerful local bus controller (TBC)

? 16 I/O signals for generic use

? Temperature of the operating junction

? WB-TePBGA II, 689-pin, 31 x 31 mm (wire bond temperature-enhanced plastic BGA)