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  • SCAN18374TSSCX

SCAN18374TSSCX

4.5V~5.5V 100MHz D-Type Flip Flop 18374 16μA SCAN Series 56-BSSOP (0.295, 7.50mm Width)


  • Manufacturer: ON Semiconductor
  • Origchip NO: 598-SCAN18374TSSCX
  • Package: 56-BSSOP (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 928
  • Description: 4.5V~5.5V 100MHz D-Type Flip Flop 18374 16μA SCAN Series 56-BSSOP (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 56-BSSOP (0.295, 7.50mm Width)
Supplier Device Package 56-SSOP
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series SCAN
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 4.5V~5.5V
Base Part Number 18374
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 2
Clock Frequency 100MHz
Current - Quiescent (Iq) 16μA
Current - Output High, Low 24mA 48mA
Number of Bits per Element 9
Max Propagation Delay @ V, Max CL 10.3ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4pF

SCAN18374TSSCX Overview


The flip flop is packaged in 56-BSSOP (0.295, 7.50mm Width). Package Tape & Reel (TR)embeds it. The output it is configured with uses Tri-State, Non-Inverted. Positive Edgeis the trigger it is configured with. There is an electrical part that is mounted in the way of Surface Mount. Powered by a 4.5V~5.5Vvolt supply, it operates as follows. In the operating environment, the temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. It belongs to the SCANseries of FPGAs. Its output frequency should not exceed 100MHz. The list contains 2 elements. As a result, it consumes 16μA quiescent current and is not affected by external forces. D latch belongs to the 18374 family. This T flip flop has a capacitance of 4pF farads at the input.

SCAN18374TSSCX Features


Tape & Reel (TR) package
SCAN series

SCAN18374TSSCX Applications


There are a lot of ON Semiconductor SCAN18374TSSCX Flip Flops applications.

  • Functionally equivalent to the MC10/100EL29
  • Registers
  • Guaranteed simultaneous switching noise level
  • Shift Registers
  • High Performance Logic for test systems
  • Balanced Propagation Delays
  • Cold spare funcion
  • Load Control
  • Circuit Design
  • Common Clocks