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  • SN74AHC374DGVR

SN74AHC374DGVR

2V~5.5V 120MHz D-Type Flip Flop 4μA 74AHC Series 20-TFSOP (0.173, 4.40mm Width)


  • Manufacturer: Rochester Electronics, LLC
  • Origchip NO: 699-SN74AHC374DGVR
  • Package: 20-TFSOP (0.173, 4.40mm Width)
  • Datasheet: PDF
  • Stock: 606
  • Description: 2V~5.5V 120MHz D-Type Flip Flop 4μA 74AHC Series 20-TFSOP (0.173, 4.40mm Width)(Kg)

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FedEx International, 5-7 business days.

The following are some common countries' logistic time.
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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 20-TFSOP (0.173, 4.40mm Width)
Supplier Device Package 20-TVSOP
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 74AHC
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 2V~5.5V
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 1
Clock Frequency 120MHz
Current - Quiescent (Iq) 4μA
Current - Output High, Low 8mA 8mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 10.1ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4pF
RoHS Status ROHS3 Compliant

SN74AHC374DGVR Overview


The flip flop is packaged in a case of 20-TFSOP (0.173, 4.40mm Width). It is included in the package Tape & Reel (TR). T flip flop is configured with an output of Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. Surface Mountis in the way of this electric part. A voltage of 2V~5.5Vis used as the supply voltage. The operating temperature is -40°C~85°C TA. A flip flop of this type is classified as a D-Type. The FPGA belongs to the 74AHC series. Its output frequency should not exceed 120MHz. A total of 1 elements are present. There is 4μA quiescent consumption. Its input capacitance is 4pFfarads.

SN74AHC374DGVR Features


Tape & Reel (TR) package
74AHC series

SN74AHC374DGVR Applications


There are a lot of Rochester Electronics, LLC SN74AHC374DGVR Flip Flops applications.

  • Shift registers
  • Balanced 24 mA output drivers
  • Single Down Count-Control Line
  • Event Detectors
  • Set-reset capability
  • Guaranteed simultaneous switching noise level
  • Circuit Design
  • Bus hold
  • Individual Asynchronous Resets
  • Divide a clock signal by 2 or 4