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  • SN74ALVCH162820DLR

SN74ALVCH162820DLR

1.65V~3.6V 150MHz D-Type Flip Flop 40μA 74ALVCH Series 56-BSSOP (0.295, 7.50mm Width)


  • Manufacturer: Rochester Electronics, LLC
  • Origchip NO: 699-SN74ALVCH162820DLR
  • Package: 56-BSSOP (0.295, 7.50mm Width)
  • Datasheet: PDF
  • Stock: 763
  • Description: 1.65V~3.6V 150MHz D-Type Flip Flop 40μA 74ALVCH Series 56-BSSOP (0.295, 7.50mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 56-BSSOP (0.295, 7.50mm Width)
Supplier Device Package 56-SSOP
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 74ALVCH
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 1.65V~3.6V
Function Standard
Output Type Tri-State, Non-Inverted
Number of Elements 1
Clock Frequency 150MHz
Current - Quiescent (Iq) 40μA
Current - Output High, Low 12mA 12mA
Number of Bits per Element 10
Max Propagation Delay @ V, Max CL 5.4ns @ 3.3V, 50pF
Trigger Type Positive Edge
Input Capacitance 3.5pF
RoHS Status ROHS3 Compliant

SN74ALVCH162820DLR Overview


It is embeded in 56-BSSOP (0.295, 7.50mm Width) case. It is included in the package Tape & Reel (TR). T flip flop uses Tri-State, Non-Invertedas the output. Positive Edgeis the trigger it is configured with. This electronic part is mounted in the way of Surface Mount. A supply voltage of 1.65V~3.6V is required for operation. It is at -40°C~85°C TAdegrees Celsius that the system is operating. It is an electronic flip flop with the type D-Type. JK flip flop is a part of the 74ALVCHseries of FPGAs. Its output frequency should not exceed 150MHz Hz. In total, it contains 1 elements. It consumes 40μA of quiescent Input capacitance of this device is 3.5pF farads.

SN74ALVCH162820DLR Features


Tape & Reel (TR) package
74ALVCH series

SN74ALVCH162820DLR Applications


There are a lot of Rochester Electronics, LLC SN74ALVCH162820DLR Flip Flops applications.

  • Set-reset capability
  • Instrumentation
  • Parallel data storage
  • CMOS Process
  • Data Synchronizers
  • Common Clocks
  • High Performance Logic for test systems
  • Balanced Propagation Delays
  • Power down protection
  • Shift Registers