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SN74LVC374ADBRE4

1.65V~3.6V 100MHz 8 Bit D-Type Flip Flop DUAL 74LVC374 20 Pins 10μA 74LVC Series 20-SSOP (0.209, 5.30mm Width)


  • Manufacturer: Texas Instruments
  • Origchip NO: 815-SN74LVC374ADBRE4
  • Package: 20-SSOP (0.209, 5.30mm Width)
  • Datasheet: -
  • Stock: 130
  • Description: 1.65V~3.6V 100MHz 8 Bit D-Type Flip Flop DUAL 74LVC374 20 Pins 10μA 74LVC Series 20-SSOP (0.209, 5.30mm Width)(Kg)

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Details

Tags

Parameters
Factory Lead Time 6 Weeks
Lifecycle Status ACTIVE (Last Updated: 1 week ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 20-SSOP (0.209, 5.30mm Width)
Number of Pins 20
Weight 156.687814mg
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 74LVC
JESD-609 Code e4
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Type D-Type
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory FF/Latches
Packing Method TR
Technology CMOS
Voltage - Supply 1.65V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 1.8V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Base Part Number 74LVC374
Function Standard
Qualification Status Not Qualified
Output Type Tri-State, Non-Inverted
Number of Elements 1
Polarity Non-Inverting
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Number of Circuits 8
Load Capacitance 50pF
Number of Ports 2
Output Current 24mA
Number of Bits 8
Clock Frequency 100MHz
Propagation Delay 8.1 ns
Turn On Delay Time 1.5 ns
Family LVC/LCX/Z
Logic Function D-Type, Flip-Flop
Current - Quiescent (Iq) 10μA
Output Characteristics 3-STATE
Current - Output High, Low 24mA 24mA
Max Propagation Delay @ V, Max CL 7ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup 7 ns
Trigger Type Positive Edge
Input Capacitance 4pF
Number of Input Lines 2
Count Direction UNIDIRECTIONAL
Clock Edge Trigger Type Positive Edge
Height 2mm
Length 7.2mm
Width 5.3mm
Thickness 1.95mm
RoHS Status ROHS3 Compliant
Lead Free Lead Free

SN74LVC374ADBRE4 Overview


The package is in the form of 20-SSOP (0.209, 5.30mm Width). D flip flop is embedded in the Tape & Reel (TR) package. Currently, the output is configured to use Tri-State, Non-Inverted. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1.65V~3.6V. A temperature of -40°C~85°C TAis used in the operation. It is an electronic flip flop with the type D-Type. The 74LVCseries comprises this type of FPGA. It should not exceed 100MHzin its output frequency. The list contains 1 elements. Despite external influences, it consumes 10μAof quiescent current. Currently, there are 20 terminations. The 74LVC374family includes it. The D flip flop is powered by a voltage of 1.8V . The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. A device of this type belongs to the family of LVC/LCX/Z. Surface Mount mounts this electronic component. This board is designed with 20pins on it. There is a clock edge trigger type of Positive Edgeon this device. This RS flip flops is a part number FF/Latches. This flip flop is designed with 8 Bits. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). To achieve this superior flexibility, 8 circuits are used. In light of its reliable performance, this T flip flop is well suited for TR. It runs on 3.3Vvolts of power. This D flip flop is equipped with 0 ports. This T flip flop features a maximum design flexibility due to its output current of 24mA. This input has 2lines in it.

SN74LVC374ADBRE4 Features


Tape & Reel (TR) package
74LVC series
20 pins
8 Bits
3.3V power supplies

SN74LVC374ADBRE4 Applications


There are a lot of Texas Instruments SN74LVC374ADBRE4 Flip Flops applications.

  • Data storage
  • Power down protection
  • Storage Registers
  • Frequency Divider circuits
  • Shift Registers
  • Latch-up performance
  • 2 – Bit synchronous counter
  • Memory
  • Registers
  • Instrumentation